Abstract: A Single Instruction Multiple Data processor apparatus for implementing algorithms using sliding window type data is shown. The implementation shifts the elements of a Destination Vector Register (406, 606) either automatically every time the destination register value is read or in response to a specific instruction (800). The shifting of the Destination Vector Register (406, 606) allows each processing element to operate on new data. As the destination vector (406, 606) elements are shifted, a new element is provided to the vector from a Source Vector Register (404, 604).

Abstract: A method for implementation of muti-port interleaved memory systems comprising any prime number P of memory modules each of which contains a power of two memory banks. Each memory bank comprises a power of two memory locations. In this method, sequential addresses are mapped into sequential memory modules, and the addresses mapped into a given module are mapped into distinct memory locations within the module without explicit and implicit operations of division by the prime number P. The method embodies families of functions any one of which can be used for the bijective mapping of addresses into memory locations within a memory module. Furthermore, any of the functions is computable in O(1) gate delays employing O(log.sub.2 P) logic gates. A multi-port interleaved memory system with P memory modules can serve multiple requests for vectors of data, where each memory port is used to serve a request for a vector of data.

Abstract: A gameboard includes a platen having intersecting channels that define a grid of tracks. Playing pieces are movable along the tracks and are retained by a bae on the playing piece that co-operates with the re-entrant walls of the channels. The flanges of the channels extend into the interstices of the tracks to retain the playing pieces while allowing their movement through the interstices.

Abstract: An array processor is described with N processing elements, N memory modules, and an interconnection network that allows parallel access and alignment of rows, columns, diagonals, contiguous blocks, and distributed blocks of N.times.N arrays. The memory system of the array processor uses the minimum number of memory modules to achieve conflict-free memory access, and computes N addresses with O(log.sub.2 N) logic gates in O(1) time. Furthermore, the interconnection network is of multistage design with O(Nlog.sub.2 N) logic gates, and is able to align any of these vectors of data for store/fetch as well as for subsequent processing with a single pass through the network.