Patents by Inventor De Ma

De Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260081606
    Abstract: A processing chip includes a first sub-circuit, an asynchronous clock interface circuit, and a second sub-circuit. The asynchronous clock interface circuit includes a first beat conversion circuit, a first trigger circuit, and a second beat conversion circuit. A first signal end of the first sub-circuit is coupled to a trigger input end of the first trigger circuit. A trigger output end of the first trigger circuit is separately coupled to an input end of the first beat conversion circuit and an input end of the second beat conversion circuit. An output end of the first beat conversion circuit is coupled to a third signal end of the first sub-circuit. An output end of the second beat conversion circuit is coupled to a second signal end of the second sub-circuit.
    Type: Application
    Filed: November 26, 2025
    Publication date: March 19, 2026
    Inventors: De Ma, Xiaofei Jin, Kanwen Wang, Lei Jiang, Tao Liu, Jianxing Liao, Jie Cheng
  • Publication number: 20250165760
    Abstract: A neural network on-chip mapping method and apparatus based on a tabu search algorithm are provided. The method includes: constructing a tabu search table and using a heuristic-based iterative search process to select local computing cores of a network-on-chip as candidates, establishing an integer programming model and solving an optimal solution, continuously reducing an objective cost function of a mapping solution by loop iteration, and finally obtaining an approximately optimal deployment scheme.
    Type: Application
    Filed: July 31, 2023
    Publication date: May 22, 2025
    Inventors: Yukun HE, De MA, Ying LI, Shichun SUN, Ming ZHANG, Xiaofei JIN, Guoquan ZHU, Fangchao YANG, Pan LV, Shuiguang DENG, Gang PAN
  • Patent number: 12217477
    Abstract: In an object recognition method, an object recognition device obtains AER data of a to-be-recognized object, wherein the AER data includes a plurality of AER events of the to-be-recognized object, each AER event comprising a timestamp and address information. The object recognition device extracts a plurality of feature maps of the AER data. Each feature map including partial spatial information and partial temporal information of the to-be-recognized object, and the partial spatial information and the partial temporal information are obtained based on the timestamp and the address information of each AER event. The object recognition device then recognizes the to-be-recognized object based on the plurality of feature maps of the AER data.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: February 4, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Gang Pan, Qianhui Liu, Lei Jiang, Jie Cheng, Haibo Ruan, Dong Xing, Huajin Tang, De Ma
  • Publication number: 20230409890
    Abstract: The present invention discloses a neuromorphic computer supporting billions of neurons, comprising hierarchical extended architecture and algorithmic process control within the architecture; the architecture comprises multiple neuromorphic computing chips with hierarchical organization management for implementing computing tasks, each containing computing neurons and synaptic resources and forming a neural network, spike events between computing neurons within the architecture are transmitted through a hierarchical transmission mode; the algorithmic process control comprises controlling parallel processing of computing tasks within the architecture, controlling management of synchronization time within the architecture, and controlling reconstruction of neural networks within the architecture to achieve fault tolerance and robust management of computing neurons and synaptic resources. The neuromorphic computer can support spiking neural network inference calculations with a neuron scale of billions.
    Type: Application
    Filed: November 12, 2020
    Publication date: December 21, 2023
    Inventors: GANG PAN, DE MA, YITAO LI, SHUHUA DAI
  • Publication number: 20220414423
    Abstract: Disclosed are a parallel method and device for convolution computation and data loading of a neural network accelerator. The method needs two input feature maps and two convolution kernel cache blocks, and sequentially stores the input feature maps and 64 convolution kernels into cache sub-blocks according to a loading length, so as to execute convolution computation and simultaneously load data of a next group of 64 convolution kernels.
    Type: Application
    Filed: May 16, 2022
    Publication date: December 29, 2022
    Applicants: Zhejiang Lab, ZHEJIANG UNIVERSITY
    Inventors: Guoquan ZHU, De MA, Qiming LU, Junhai FAN, Fangchao YANG, Xiaofei JIN, Shichun SUN, Youneng HU
  • Publication number: 20220180619
    Abstract: In an object recognition method, an object recognition device obtains AER data of a to-be-recognized object, wherein the AER data includes a plurality of AER events of the to-be-recognized object, each AER event comprising a timestamp and address information. The object recognition device extracts a plurality of feature maps of the AER data. Each feature map including partial spatial information and partial temporal information of the to-be-recognized object, and the partial spatial information and the partial temporal information are obtained based on the timestamp and the address information of each AER event. The object recognition device then recognizes the to-be-recognized object based on the plurality of feature maps of the AER data.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Gang Pan, Qianhui Liu, Lei Jiang, Jie Cheng, Haibo Ruan, Dong Xing, Huajin Tang, De Ma