Patents by Inventor De-Ming Liang

De-Ming Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Frame layout to monitor overlay performance of chip composed of multi-exposure images
    Patent number: 6330355
    Abstract: A frame layout and method for determining the overlay accuracy of a first chip image relative to a second chip image when the first and second chip images are used to form a single chip. One embodiment employs a vernier scale in two orthoginal directions included in the scribeline of both the first chip image and the second chip image. Another embodiment employs a box in box pattern included in the scribeline of both the first chip image and the second chip image. A layer of photoresist on an integrated circuit wafer is exposed with the first and second chip image and the associated monitor images. When the photoresist is developed the overlay accuracy of the first chip image relative to the second chip image can be determined directly from the monitor images in the photoresist.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: December 11, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chia-Hsiang Chen, Chih-Chien Hung, Han-Ming Sheng, Hsiang-Chung Liu, Chun-Mei Lee, De-Ming Liang, Li-Kong Turn, Ming-Huei Tseng