Abstract: The embodiment of the present disclosure provides a display panel and a display apparatus. The display panel includes a long side, a short side, a display pixel, a scan driving circuit, a drive circuit board, and chips on film. one end of each chip on film is coupled to the short side, and another end is coupled to the drive circuit board. The drive circuit board and the scan driving circuit of the embodiment of the present disclosure are respectively located on the short side and the long side of the display panel to improve the problem that the font is easily deformed during display.

Abstract: A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.

Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.

Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.

Abstract: A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.

Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.

Abstract: The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.

Abstract: The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.

Abstract: The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region; forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.

Abstract: Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes an n-type reduced surface field, a p-type body well disposed on a lateral side of the n-type reduced surface field region, a shallow trench isolation structure disposed within the n-type reduced surface field region, and a gate structure disposed partially over the p-type body well, partially over the n-type reduced surface field region, partially over the shallow trench isolation structure, and partially within the shallow trench isolation structure.

Abstract: The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region: forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.

Abstract: Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes a p-type semiconductor substrate, an n-type epitaxial layer disposed over and in contact with the p-type semiconductor substrate, and a p-type implant layer disposed within the n-type epitaxial layer, wherein the p-type implant layer is not in contact with the p-type semiconductor substrate. It further includes an n-type reduced surface field region disposed over and in contact with the p-type implant layer, a p-type body well disposed on a lateral side of the p-type implant layer and the n-type reduced surface field region, and a shallow trench isolation (STI) structure disposed within the n-type reduced surface field region. Still further, it includes a gate structure disposed partially over the p-type body well, partially over the n-type surface field region, and partially over the STI structure.

Abstract: Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes an n-type reduced surface field, a p-type body well disposed on a lateral side of the n-type reduced surface field region, a shallow trench isolation structure disposed within the n-type reduced surface field region, and a gate structure disposed partially over the p-type body well, partially over the n-type reduced surface field region, partially over the shallow trench isolation structure, and partially within the shallow trench isolation structure.

Abstract: Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes a p-type semiconductor substrate, an n-type epitaxial layer disposed over and in contact with the p-type semiconductor substrate, and a p-type implant layer disposed within the n-type epitaxial layer, wherein the p-type implant layer is not in contact with the p-type semiconductor substrate. It further includes an n-type reduced surface field region disposed over and in contact with the p-type implant layer, a p-type body well disposed on a lateral side of the p-type implant layer and the n-type reduced surface field region, and a shallow trench isolation (STI) structure disposed within the n-type reduced surface field region. Still further, it includes a gate structure disposed partially over the p-type body well, partially over the n-type surface field region, and partially over the STI structure.

Abstract: Integrated circuits with improved LDMOS structures are provided. An integrated circuit includes a semiconductor substrate, a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate. The integrated circuit further includes a transistor structure. The transistor structure includes a gate dielectric positioned over a portion of a first one of the plurality of STI regions, a drain region adjacent to the first one of the plurality of STI regions and spaced apart from the gate dielectric, a first gate electrode that extends over a first portion of the gate dielectric, a second gate electrode that extends over a second portion of the gate dielectric and positioned adjacent to the first gate electrode, and a source region positioned adjacent to the first portion of the gate dielectric.

Abstract: Integrated circuits with improved LDMOS structures are provided. An integrated circuit includes a semiconductor substrate, a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate. The integrated circuit further includes a transistor structure. The transistor structure includes a gate dielectric positioned over a portion of a first one of the plurality of STI regions, a drain region adjacent to the first one of the plurality of STI regions and spaced apart from the gate dielectric, a first gate electrode that extends over a first portion of the gate dielectric, a second gate electrode that extends over a second portion of the gate dielectric and positioned adjacent to the first gate electrode, and a source region positioned adjacent to the first portion of the gate dielectric.

Abstract: A method for forming a low Rdson LDNMOS and a high sheet resistance poly resistor and the resulting device are provided. Embodiments include forming first, second, and third STI regions in a substrate; forming a P-well in the substrate around the first STI region with a first mask; forming an N-drift region in the substrate between the P-well and the third STI region with the first mask; forming a dielectric layer over the substrate; forming a poly-silicon layer over the dielectric layer; performing an N-drain implant between the second and third STI regions with a second mask; performing a resistance adjustment implant in, but not through, the poly-silicon layer with the second mask; and patterning the poly-silicon and dielectric layers subsequent to performing the resistance adjustment implant to form a gate stack and a poly resistor, the poly resistor being formed over the third STI region and laterally separated from the gate stack.

Abstract: A method for forming a low Rdson LDNMOS and a high sheet resistance poly resistor and the resulting device are provided. Embodiments include forming first, second, and third STI regions in a substrate; forming a P-well in the substrate around the first STI region with a first mask; forming an N-drift region in the substrate between the P-well and the third STI region with the first mask; forming a dielectric layer over the substrate; forming a poly-silicon layer over the dielectric layer; performing an N-drain implant between the second and third STI regions with a second mask; performing a resistance adjustment implant in, but not through, the poly-silicon layer with the second mask; and patterning the poly-silicon and dielectric layers subsequent to performing the resistance adjustment implant to form a gate stack and a poly resistor, the poly resistor being formed over the third STI region and laterally separated from the gate stack.