Patents by Inventor De-Yuan Lu
De-Yuan Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240061339Abstract: A photoresist apparatus and a method are provided. The photoresist apparatus includes a pre-baking apparatus. The pre-baking apparatus includes: a hot-plate, a first cover over the hot-plate, a second cover over the first cover, a first heating element extending along a topmost surface of the first cover, and a second heating element extending along a topmost surface of the second cover.Type: ApplicationFiled: November 3, 2023Publication date: February 22, 2024Inventors: Hung-Jui Kuo, De-Yuan Lu, Chen-Hua Yu, Ming-Tan Lee
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Patent number: 11848233Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.Type: GrantFiled: March 27, 2022Date of Patent: December 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
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Patent number: 11841618Abstract: A photoresist apparatus and a method are provided. The photoresist apparatus includes a pre-baking apparatus. The pre-baking apparatus includes: a hot-plate, a first cover over the hot-plate, a second cover over the first cover, a first heating element extending along a topmost surface of the first cover, and a second heating element extending along a topmost surface of the second cover.Type: GrantFiled: January 3, 2022Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Jui Kuo, De-Yuan Lu, Chen-Hua Yu, Ming-Tan Lee
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Patent number: 11823969Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.Type: GrantFiled: June 30, 2022Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
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Publication number: 20230369153Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.Type: ApplicationFiled: July 28, 2023Publication date: November 16, 2023Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
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Patent number: 11515224Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.Type: GrantFiled: January 17, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
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Publication number: 20220336307Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
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Publication number: 20220216103Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.Type: ApplicationFiled: March 27, 2022Publication date: July 7, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
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Publication number: 20220121120Abstract: A photoresist apparatus and a method are provided. The photoresist apparatus includes a pre-baking apparatus. The pre-baking apparatus includes: a hot-plate, a first cover over the hot-plate, a second cover over the first cover, a first heating element extending along a topmost surface of the first cover, and a second heating element extending along a topmost surface of the second cover.Type: ApplicationFiled: January 3, 2022Publication date: April 21, 2022Inventors: Hung-Jui Kuo, De-Yuan Lu, Chen-Hua Yu, Ming-Tan Lee
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Patent number: 11289373Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.Type: GrantFiled: July 7, 2019Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
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Patent number: 11215929Abstract: A photoresist apparatus and a method are provided. The photoresist apparatus includes a pre-baking apparatus. The pre-baking apparatus includes: a hot-plate, a first cover over the hot-plate, a second cover over the first cover, a first heating element extending along a topmost surface of the first cover, and a second heating element extending along a topmost surface of the second cover.Type: GrantFiled: December 21, 2018Date of Patent: January 4, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, De-Yuan Lu, Chen-Hua Yu, Ming-Tan Lee
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Publication number: 20210225722Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
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Publication number: 20210118697Abstract: A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Inventors: Hung-Jui Kuo, Ming-Tan Lee, Chen-Cheng Kuo, De-Yuan Lu
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Patent number: 10861710Abstract: A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening.Type: GrantFiled: October 1, 2018Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Ming-Tan Lee, Chen-Cheng Kuo, De-Yuan Lu
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Publication number: 20200133128Abstract: A photoresist apparatus and a method are provided. The photoresist apparatus includes a pre-baking apparatus. The pre-baking apparatus includes: a hot-plate, a first cover over the hot-plate, a second cover over the first cover, a first heating element extending along a topmost surface of the first cover, and a second heating element extending along a topmost surface of the second cover.Type: ApplicationFiled: December 21, 2018Publication date: April 30, 2020Inventors: Hung-Jui Kuo, De-Yuan Lu, Chen-Hua Yu, Ming-Tan Lee
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Publication number: 20200043782Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.Type: ApplicationFiled: July 7, 2019Publication date: February 6, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
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Publication number: 20200006086Abstract: A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening.Type: ApplicationFiled: October 1, 2018Publication date: January 2, 2020Inventors: Hung-Jui Kuo, Ming-Tan Lee, Chen-Cheng Kuo, De-Yuan Lu
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Patent number: 9449931Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.Type: GrantFiled: August 25, 2014Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chung Lin, Chung-Shi Liu, Meng-Wei Chou, Kuo Cheng Lin, Wen-Hsiung Lu, Chien Ling Hwang, Ying-Jui Huang, De-Yuan Lu
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Patent number: 9397080Abstract: A method of packaging semiconductor dies may include: coupling a first die to a first substrate; forming a plurality of first portions of a plurality of metal pillars on a surface of the first substrate; forming a second portion of the plurality of metal pillars over each of the plurality of first portions of the plurality of metal pillars; forming a protection layer over sidewalls of each of the plurality of first portions and second portions of the plurality of metal pillars; coupling a second die to a second substrate; and coupling the plurality of metal pillars to the second substrate.Type: GrantFiled: March 13, 2015Date of Patent: July 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Lei Hsu, Yu-Feng Chen, Ming-Che Ho, De-Yuan Lu, Chung-Shi Liu
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Publication number: 20150187746Abstract: A method of packaging semiconductor dies may include: coupling a first die to a first substrate; forming a plurality of first portions of a plurality of metal pillars on a surface of the first substrate; forming a second portion of the plurality of metal pillars over each of the plurality of first portions of the plurality of metal pillars; forming a protection layer over sidewalls of each of the plurality of first portions and second portions of the plurality of metal pillars; coupling a second die to a second substrate; and coupling the plurality of metal pillars to the second substrate.Type: ApplicationFiled: March 13, 2015Publication date: July 2, 2015Inventors: Chun-Lei Hsu, Yu-Feng Chen, Ming-Che Ho, De-Yuan Lu, Chung-Shi Liu