Patents by Inventor De-Zhang Deng

De-Zhang Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11444206
    Abstract: A manufacturing method of a semiconductor structure including the following steps is provided: forming a first metal layer on a substrate; forming an insulating layer on the first metal layer; forming an oxide semiconductor material layer on the insulating layer; performing an annealing treatment to the oxide semiconductor material layer; forming an etch stopping material layer on the oxide semiconductor material layer; forming a photoresist material layer on the etch stopping material layer and defining thereof with a half tone photomask to form a photoresist pattern; using the photoresist pattern as a mask, patterning the etch stopping material layer to form an etch stopping pattern, and patterning the oxide semiconductor material layer to form an oxide semiconductor layer; removing the photoresist pattern; using the etch stopping pattern as the mask, patterning the insulating layer; forming a second metal layer on the etch stopping pattern; and patterning the oxide semiconductor layer.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: September 13, 2022
    Assignee: Au Optronics Corporation
    Inventors: Po-Liang Yeh, Chen-Chung Wu, De-Zhang Deng, Chia-Ming Chang
  • Publication number: 20210367079
    Abstract: A manufacturing method of a semiconductor structure including the following steps is provided: forming a first metal layer on a substrate; forming an insulating layer on the first metal layer; forming an oxide semiconductor material layer on the insulating layer; performing an annealing treatment to the oxide semiconductor material layer; forming an etch stopping material layer on the oxide semiconductor material layer; forming a photoresist material layer on the etch stopping material layer and defining thereof with a half tone photomask to form a photoresist pattern; using the photoresist pattern as a mask, patterning the etch stopping material layer to form an etch stopping pattern, and patterning the oxide semiconductor material layer to form an oxide semiconductor layer; removing the photoresist pattern; using the etch stopping pattern as the mask, patterning the insulating layer; forming a second metal layer on the etch stopping pattern; and patterning the oxide semiconductor layer.
    Type: Application
    Filed: August 5, 2021
    Publication date: November 25, 2021
    Applicant: Au Optronics Corporation
    Inventors: Po-Liang Yeh, Chen-Chung Wu, De-Zhang Deng, Chia-Ming Chang
  • Patent number: 11171244
    Abstract: A semiconductor structure disposed on a substrate including a first metal layer disposed on the substrate, a gate insulating layer disposed on the substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopping pattern disposed on the oxide semiconductor layer, and a second metal layer disposed on the etch stopping layer. The first metal layer includes a gate line. The gate insulating layer covers the gate line. Patterning of the oxide semiconductor layer defines an oxide semiconductor pattern. The second metal layer includes a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern. The etch stopping layer is located between the second metal layer and the oxide semiconductor layer. The second metal layer includes a signal line disposed on the etch stopping layer and is electrically connected to the oxide semiconductor pattern. A manufacturing method of the semiconductor structure is also provided.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: November 9, 2021
    Assignee: Au Optronics Corporation
    Inventors: Po-Liang Yeh, Chen-Chung Wu, De-Zhang Deng, Chia-Ming Chang
  • Publication number: 20200303553
    Abstract: A semiconductor structure disposed on a substrate including a first metal layer disposed on the substrate, a gate insulating layer disposed on the substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopping pattern disposed on the oxide semiconductor layer, and a second metal layer disposed on the etch stopping layer. The first metal layer includes a gate line. The gate insulating layer covers the gate line. Patterning of the oxide semiconductor layer defines an oxide semiconductor pattern. The second metal layer includes a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern. The etch stopping layer is located between the second metal layer and the oxide semiconductor layer. The second metal layer includes a signal line disposed on the etch stopping layer and is electrically connected to the oxide semiconductor pattern. A manufacturing method of the semiconductor structure is also provided.
    Type: Application
    Filed: July 4, 2019
    Publication date: September 24, 2020
    Applicant: Au Optronics Corporation
    Inventors: Po-Liang Yeh, Chen-Chung Wu, De-Zhang Deng, Chia-Ming Chang