Abstract: A device may receive data related to a material. The data may permit an analysis of an exposure related to the material. The data may be received from another device. The device may process the data to determine a category of materials for the material. The category of materials may indicate a set of exposures, related to the material, to an organization. The device may process the data to determine an exposure preparedness level associated with the material. The exposure preparedness level may indicate a preparedness of the organization to handle the set of exposures related to the material. The device may determine a score for the material based on the category of materials and the exposure preparedness level associated with the material. The score may indicate the exposure related to the material. The device may perform an action related to the material based on the score for the material.

Abstract: A device may receive data related to a material. The data may permit an analysis of an exposure related to the material. The data may be received from another device. The device may process the data to determine a category of materials for the material. The category of materials may indicate a set of exposures, related to the material, to an organization. The device may process the data to determine an exposure preparedness level associated with the material. The exposure preparedness level may indicate a preparedness of the organization to handle the set of exposures related to the material. The device may determine a score for the material based on the category of materials and the exposure preparedness level associated with the material. The score may indicate the exposure related to the material. The device may perform an action related to the material based on the score for the material.

Abstract: A device and method for the protection of individuals in a room having an outward swinging door is presented. The device includes a central chamber for the surrounding of a door handle, a first flange for extension from the central chamber and contacting the door, and a second flange for extension from the central chamber and contacting the door frame. The two flanges are relatively parallel and create a binding force around the handle as the door is opened, such that the door is prevented from opening. An optional slot is included to accommodate handles with levers. In operation, the device is lowered over the handle and held in place by gravity. It symmetric design allows it to function with both left handed and right handed opening outward doors.

Abstract: A method and apparatus for managing virtual objects in a network is provided. The method includes creating a unique link between at least one virtual object and a physical token. The at least one virtual object is represented by a first set of distinct predefined properties and is associated with a data set. Further, the method includes maintaining information about the unique link between the at least one virtual object and the physical token and information about the first set of distinct predefined properties. Furthermore, the method includes regulating access to the at least one virtual object based on a second set of predefined properties and verification of the physical token.

Abstract: Bank card fraud detection and/or prevention methods can generally involve determining a common point of compromise and/or identifying merchants associated with bank card transaction frequencies which exceed a predetermined threshold value which is indicative of potentially fraudulent bank card activity. These methods can further involve identifying other bank cards used at the common point of compromise.

Abstract: The subject application provides methods for the direct or indirect improvement of levels of key phytonutrients and/or stress tolerance in plants. Methods of providing for the improvement in key phytonutrient levels and/or stress tolerance in plants are provided through the application of safeners, herbicides, fungicides, insecticides, nematicides, miticides, defoliants/desiccants, antibiotics, and/or plant growth regulators to plants. Agricultural products arising from the disclosed methods are also provided.

Abstract: The present disclosure provides methods and systems for purifying an impaired liquid. In a particular example, the disclosure provides methods and systems for purifying water containing a solute. A feed stream of solute containing water is introduced in a flow chamber. A permeate stream of water at least substantially free of the solute is placed in the flow chamber. A hydrophobic membrane is placed between the feed stream and the permeate stream. A vacuum is applied to the permeate stream. A vapor pressure differential causes water to vaporize from the feed stream, pass through the hydrophobic membrane, and condense in the permeate stream.

Abstract: The present disclosure provides methods and systems for purifying an impaired liquid. In a particular example, the disclosure provides methods and systems for purifying water containing a solute. A feed stream of solute containing water is introduced in a flow chamber. A permeate stream of water at least substantially free of the solute is placed in the flow chamber. A hydrophobic membrane is placed between the feed stream and the permeate stream. A vacuum is applied to the permeate stream. A vapor pressure differential causes water to vaporize from the feed stream, pass through the hydrophobic membrane, and condense in the permeate stream.

Abstract: Automatically characterizing a behavior of an object or objects by processing object data to obtain a data set that records a measured parameter set for each object over lime, providing a learning input that identifies when the measured parameter set of an object is associated with a behavior, processing the data set in combination with the learning input to determine which parameters of the parameter set over which range of respective values characterize the behavior; and sending information that identifies which parameters of the parameter set over which range of respective values characterize the behavior for use in a process that uses the characteristic parameters and their characteristic ranges to process second object data and automatically identify when the behavior occurs. Also disclosed is a method of tracking one or more objects.

Abstract: A method and apparatus for managing virtual objects in a network is provided. The method includes creating a unique link between at least one virtual object and a physical token. The at least one virtual object is represented by a first set of distinct predefined properties and is associated with a data set. Further, the method includes maintaining information about the unique link between the at least one virtual object and the physical token and information about the first set of distinct predefined properties. Furthermore, the method includes regulating access to the at least one virtual object based on a second set of predefined properties and verification of the physical token.

Abstract: Bank card fraud detection and/or prevention methods can generally involve determining a common point of compromise and/or identifying merchants associated with bank card transaction frequencies which exceed a predetermined threshold value which is indicative of potentially fraudulent bank card activity. These methods can further involve identifying other bank cards used at the common point of compromise.

Abstract: The present invention provides a method and apparatus for determining a root cause of a fault. The method includes detecting at least one fault associated with at least one first wafer processed according to a first processing context and processing at least one second wafer according to at least one second processing context. The second processing context is different than the first processing context. The method also includes determining a root cause associated with the fault based on the first processed wafer and the second processed wafer.

Abstract: A BIST system that utilizes ECC to correct single bit errors in a given memory word at a given address, the ECC having a maximum number of bit errors it can correct in the given memory word. A first set of gates is coupled to an array of memory cells that stores a plurality of memory words, each at a given address. The first set of gates provides bit outputs indicative of errors in a given memory word while the given memory word is under test. A circuit coupled to respective outputs of the first set of gates determines if a number of errors in the memory word under test exceeds the maximum number of errors correctable by the ECC.

Abstract: A memory logic built-in self-test (“BIST”) includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller is configured to include control features and address, data, read/write, output evaluation, and redundancy calculation values are configured within the collars. The controller is further configured to handle scheduling of the collars and diagnostics interfacing. In addition, the collars are configured to allow BIST testing to be run serially, in parallel, or in groups. Collars are also configured to send diagnostic results back to the controller based on the initialization of the respective collars, thus providing a central interface for the diagnostics results.

Abstract: A microcode programmable built-in-self-test (BIST) circuit and method for testing a multiported memory via multiple ports, either simultaneously or sequentially, as directed by a microcode instruction word. The microcode instruction word contains a plurality of executable subinstructions and one bit of information that controls whether the test operations prescribed in the plurality of subinstructions shall be executed in parallel or in series. The executable subinstructions are dispatched by a primary controller to subcontrollers which perform test operations at each port according to the subinstructions. The microcode programable BIST architecture flexibly facilitates the testing of multiple devices, multiported devices, including multiported memory structures and complex dependent multiported memory structures. The BIST supports in-situ testing of the functionality of the memory at wafer, module, and burn-in, as well as system-level testing.

Abstract: A fault recovery system for an array of memory cells. A register stores data indicating addresses of multi-cell fails and single-cell fails. A first fault correction system accesses data from the register to fix both multi-cell fails and single-cell fails. A second fault correction system does not access said register and fixes single-cell fails. During testing, if a multi-cell fail is detected the register stores its address by deleting an address of a single-cell fail if the register is full.

Abstract: A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.

Abstract: A system and methodology for testing memory in an integrated circuit implementing BIST testing to calculate row and column redundancy and enable replacement of a defective row or column of memory cells. The system comprises circuitry for detecting a first single memory cell failure in a row; and, recording the I/O value of the first Single Cell Fail (SCF). A circuit is provided for detecting whether more than one single cell failure has occurred for a tested row, and, in response to detecting a second SCF, comparing recorded I/O value of the subsequent tested row, with the I/O value associated with the first failed memory cell. Upon detection of defective bits, the defective column and row of memory having corresponding defective bits set is replaced.

Abstract: A built-in self test system (124) and method for two-dimensional memory redundancy allocation. The built-in self test system is adapted to allocate two redundant columns (116) and one redundant row (120) to an embedded memory (104) as needed to repair single cell failures (SCFs) within the rows (108) and columns of the memory. The self-test system includes a left-priority encoder (136), a right-priority encoder (140), and a greater-than-two detector (144). The left-priority encoder encodes the location of the first SCF most proximate the most-significant bit of the corresponding word. The right-priority encoder encodes the location of the first SCF most proximate the least-significant bit of the corresponding word. The greater-than-two detector determines whether a word contains more than two SCFs.

Abstract: The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in service in larger systems, by generating default test signals which are loaded in an instruction store module when test instructions are not provided from an external tester. This additional utility of the BIST arrangement, increases efficiency of chip space utilization and improves the system level test. Loading of test instructions from an external tester during chip manufacture and/or board assembly is unaffected.