Patents by Inventor Dean D. Gans

Dean D. Gans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220246186
    Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
  • Patent number: 11403241
    Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 11397679
    Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 11381432
    Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Publication number: 20220188035
    Abstract: Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 16, 2022
    Inventor: Dean D. Gans
  • Publication number: 20220187988
    Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 16, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Dean D. Gans, Shunichi Saito
  • Patent number: 11355169
    Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
  • Patent number: 11340830
    Abstract: Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
  • Publication number: 20220148640
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a multi-bit duty cycle monitor. A clock signal may be provided to a memory in order to synchronize one or more operations of the memory. The clock signal may have a duty cycle which is adjusted by a duty cycle adjustor of the memory. The duty cycle of the adjusted clock signal may be monitored by a multi-bit duty cycle monitor. The multi-bit duty cycle monitor may provide a multi-bit signal which indicates if the duty cycle of the adjusted clock signal is above or below a target duty cycle value (or if the duty cycle is outside tolerances around the target duty cycle). The multi-bit duty cycle monitor may provide the multi-bit signal while access operations of the memory are occurring.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 12, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Dean D. Gans
  • Publication number: 20220149828
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.
    Type: Application
    Filed: October 14, 2021
    Publication date: May 12, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Dean D. Gans
  • Patent number: 11209981
    Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Shunichi Saito
  • Patent number: 11210019
    Abstract: Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 11194726
    Abstract: Methods, systems, and devices for stacked memory dice and combined access operations are described. A device may include multiple memory dice. One die may be configured as a master, and another may be configured as a slave. The master may communicate with a host device. A slave may be coupled with the master but not the host device. The device may include a first die (e.g., master) and a second die (e.g., slave). The first die may be coupled with a host device and configured to output a set of data in response to a read command. The first die may supply a first subset of the data and obtain a second subset of the data from the second die. In some cases, the first die may select, based on a data rate, a modulation scheme (e.g., PAM4, NRZ, etc.) and output the data using the selected modulation scheme.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 11189334
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a multi-bit duty cycle monitor. A clock signal may be provided to a memory in order to synchronize one or more operations of the memory. The clock signal may have a duty cycle which is adjusted by a duty cycle adjustor of the memory. The duty cycle of the adjusted clock signal may be monitored by a multi-bit duty cycle monitor. The multi-bit duty cycle monitor may provide a multi-bit signal which indicates if the duty cycle of the adjusted clock signal is above or below a target duty cycle value (or if the duty cycle is outside tolerances around the target duty cycle). The multi-bit duty cycle monitor may provide the multi-bit signal while access operations of the memory are occurring.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Publication number: 20210357137
    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 18, 2021
    Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
  • Publication number: 20210358539
    Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Timothy B. Cowles, Dean D. Gans, Jiyun Li, Nathaniel J. Meier, Randall J. Rooney
  • Publication number: 20210326072
    Abstract: Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.
    Type: Application
    Filed: May 4, 2021
    Publication date: October 21, 2021
    Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
  • Patent number: 11152929
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 11150821
    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
  • Publication number: 20210287724
    Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.
    Type: Application
    Filed: April 6, 2021
    Publication date: September 16, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Dean D. Gans, Daniel C. Skinner