Abstract: A semiconductor device (10) is formed having an SRAM array with a plurality of SRAM cells. In forming the access and latch transistors, two different gate electrode compositions are used to form the access and latch transistors. More specifically, a dielectric layer (22) is formed between two conductive layers (26 and 28) within the gate electrode (52) for the access transistors while the dielectric layer is not formed between the two conductive layers (26 and 28) for the latch transistors. This structure allows an increase in the beta ratio for the SRAM cell thereby making a more stable SRAM cell without having to use diffused resistors between the access transistors in storage nodes or by having to form a differential thickness between the gate dielectric layers for the latch transistors and the access transistors.