Patents by Inventor Dean Eshleman

Dean Eshleman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8471254
    Abstract: A laminate structure and method of manufacture, such as a processed silicon wafer with an overlying layer or cover, includes a first layer or substrate which has a generally-planar region and a peripheral contoured region with falloff from a planar region of the first layer, and a second layer which overlies the first layer and is spaced from the planar region of the first layer a uniform distance by a plurality of uniform spacers, and peripheral spacers located in the peripheral contoured region which extend from the first layer to the second layer to maintain the second layer in the same plane as it extends over the falloff of the peripheral contoured region of the first layer to increase the useable area of the laminate structure. Spherical, deformable and fixed dimension spacers are used.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: June 25, 2013
    Assignee: Hana Microdisplay Technologies, Inc.
    Inventor: Dean Eshleman
  • Patent number: 7320930
    Abstract: Wafer scale and substrate processing device singulation methods, and devices made by the methods, for singulation of discrete devices from a processed wafer or laminated structures, involves formation of separation scribes or saw cuts at multiple elevations in intersecting scribe streets or lines so that a separation cut in one direction is at a different depth than a separation cut in a different and intersecting direction. Separation or fracture of the wafer or laminated structure along one of the separation cuts does not transfer to the separation line of the intersecting separation cut due to the difference in depth of the intersecting cuts or scribes, and due to the difference in elevation of the bottom surfaces of the cuts or scribes within the scribe streets, resulting in cleaner edges on the separated devices.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: January 22, 2008
    Assignee: HANA Microdisplay Technologies, Inc.
    Inventor: Dean Eshleman
  • Publication number: 20070158863
    Abstract: A laminate structure and method of manufacture, such as a processed silicon wafer with an overlying layer or cover, includes a first layer or substrate which has a generally-planar region and a peripheral contoured region with falloff from a planar region of the first layer, and a second layer which overlies the first layer and is spaced from the planar region of the first layer a uniform distance by a plurality of uniform spacers, and peripheral spacers located in the peripheral contoured region which extend from the first layer to the second layer to maintain the second layer in the same plane as it extends over the falloff of the peripheral contoured region of the first layer to increase the useable area of the laminate structure. Spherical, deformable and fixed dimension spacers are used.
    Type: Application
    Filed: December 27, 2005
    Publication date: July 12, 2007
    Inventor: Dean Eshleman
  • Publication number: 20060250564
    Abstract: A laminate, and a method of forming a laminate that includes a first substrate coupled to a second substrate to define a cavity having a predetermined cell gap, and a continuous seal disposed between the substrates that extends about the entire periphery of the laminate and is substantially devoid of apertures. The substrates are joined together by a peripheral seal in a relatively low pressure environment and then relocated to a relatively higher pressure environment to establish a cell gap between the substrates by the relative change in ambient pressure.
    Type: Application
    Filed: May 9, 2005
    Publication date: November 9, 2006
    Inventor: Dean Eshleman
  • Publication number: 20050233549
    Abstract: Wafer scale and substrate processing device singulation methods, and devices made by the methods, for singulation of discrete devices from a processed wafer or laminated structures, involves formation of separation scribes or saw cuts at multiple elevations in intersecting scribe streets or lines so that a separation cut in one direction is at a different depth than a separation cut in a different and intersecting direction. Separation or fracture of the wafer or laminated structure along one of the separation cuts does not transfer to the separation line of the intersecting separation cut due to the difference in depth of the intersecting cuts or scribes, and due to the difference in elevation of the bottom surfaces of the cuts or scribes within the scribe streets, resulting in cleaner edges on the separated devices.
    Type: Application
    Filed: April 19, 2004
    Publication date: October 20, 2005
    Inventor: Dean Eshleman