Patents by Inventor Dean G. Percy

Dean G. Percy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8689066
    Abstract: A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Grady, Mark C. Johnson, Bradley D. Pepper, Dean G. Percy, Joseph C. Pranys
  • Publication number: 20130007546
    Abstract: A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew S. Grady, Mark C. Johnson, Bradley D. Pepper, Dean G. Percy, Joseph C. Pranys
  • Patent number: 7058531
    Abstract: A method is disclosed of temperature compensation for measurement of a temperature sensitive parameter of semiconductor IC chips, particularly temperature compensation for a maximum frequency measurement (Fmax) and speed sort/categorization of semiconductor IC chips. The method includes determining a change of a temperature sensitive parameter of the chip with temperature; measuring the temperature sensitive parameter of the chip during testing of the chip; measuring the chip temperature directly during or following the measurement of the temperature sensitive parameter; and determining an adjusted temperature sensitive parameter of the chip based upon the measured temperature sensitive parameter of the chip during testing, the measured chip temperature, and the determined change of the temperature sensitive parameter of the chip with temperature.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: June 6, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jennifer E. Appleyard, Troy Carlson, Joseph M. Forbes, Dean G. Percy, Norman J. Rohrer, William J. Tanona