Patents by Inventor Dean Gans

Dean Gans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10796746
    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner
  • Patent number: 10789186
    Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Dean Gans
  • Publication number: 20200287778
    Abstract: According to one embodiment, a data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Timothy M. Hollis, Dean Gans, Randon Richards, Bruce W. Schober
  • Publication number: 20200252069
    Abstract: Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 6, 2020
    Applicant: Micron Technology, Inc.
    Inventor: Dean Gans
  • Patent number: 10700918
    Abstract: According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Timothy M. Hollis, Dean Gans, Randon Richards, Bruce W. Schober
  • Publication number: 20200126608
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a first power supply having a first fixed voltage, a second power supply having a second fixed voltage, a plurality of circuits coupled to the first power supply via a first switch and the second power supply via a second switch, and a power control circuit configured to selectively enable one of the first switch and the second switch responsive to power demand information.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Applicant: Micron Technology, Inc.
    Inventor: Dean Gans
  • Patent number: 10615798
    Abstract: Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Dean Gans
  • Publication number: 20200050564
    Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kang-Yong Kim, Dean Gans
  • Patent number: 10541019
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a first power supply having a first fixed voltage, a second power supply having a second fixed voltage, a plurality of circuits coupled to the first power supply via a first switch and the second power supply via a second switch, and a power control circuit configured to selectively enable one of the first switch and the second switch responsive to power demand information.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: January 21, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Dean Gans
  • Patent number: 10467158
    Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Dean Gans
  • Publication number: 20190334505
    Abstract: Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Applicant: Micron Technology, Inc.
    Inventor: Dean Gans
  • Patent number: 10394473
    Abstract: An arbitration system and method is disclosed. The apparatus includes a first and a second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device includes a first calibration circuit configured to perform a first calibration operation responsive, at least in part, to an external calibration command, the first calibration operation being performed based on the resistor, and the second memory device includes a second calibration circuit configured to perform a second calibration operation responsive, at least in part, to the external calibration command, the second calibration operation being performed based on the resistor after the first calibration operation has finished.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Dean Gans
  • Patent number: 10387341
    Abstract: Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dean Gans, Bruce Schober, Moo Sung Chae
  • Patent number: 10348270
    Abstract: Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Dean Gans
  • Publication number: 20190163652
    Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.
    Type: Application
    Filed: July 13, 2018
    Publication date: May 30, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kang-Yong Kim, Dean Gans
  • Publication number: 20190163653
    Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.
    Type: Application
    Filed: July 13, 2018
    Publication date: May 30, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kang-Yong Kim, Dean Gans
  • Publication number: 20190131972
    Abstract: Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.
    Type: Application
    Filed: June 14, 2018
    Publication date: May 2, 2019
    Applicant: Micron Technology, Inc.
    Inventor: Dean Gans
  • Publication number: 20190109755
    Abstract: According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 11, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Timothy M. Hollis, Dean Gans, Randon Richards, Bruce W. Schober
  • Publication number: 20190087366
    Abstract: Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.
    Type: Application
    Filed: November 16, 2018
    Publication date: March 21, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Dean Gans, Bruce Schober, Moo Sung Chae
  • Publication number: 20190027208
    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 24, 2019
    Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner