Abstract: Embodiments relate to a system, program product, and method for validating a system under test (SUT). The method includes selecting one or more random biases for one or more properties of the one or more API requests. The method also includes transmitting the one or more API requests to the SUT, transmitting an API response from the SUT for each of the one or more API requests, and validating each API response.

Abstract: Embodiments relate to a system, program product, and method for validating a system under test (SUT). The method includes selecting one or more random biases for one or more properties of the one or more API requests. The method also includes transmitting the one or more API requests to the SUT, transmitting an API response from the SUT for each of the one or more API requests, and validating each API response.

Abstract: A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

Abstract: Method and program product for analyzing an asynchronously clocked system. The system being analyzed has independently clocked subsystems with clock boundaries therebetween. The model identifies a boundary between the two independently clocked subsystems, and identifies behavior at the boundary between the two independently clocked subsystems. and modeling a latch at the boundary between the two independently clocked subsystems with a behavior model, said behavioral model comprising data receiver time delays.

Abstract: A. system (i.e. a tool set) provides logic verification at the logic design level in which an external stimulus to the design is derived from a series of generalized timing diagrams that obey the interface protocols of the logic design under test. A timing diagram editor provides a graphical user interface that allows the logic designer to describe his or her logic in a general timing diagram format incorporating permutations of the interface specification. The output of the timing diagram editor is a file that describes the interfaces of the logic; this file can contain multiple timing diagrams that describe different interface interactions. A suitable simulation driver reads the file created by the timing diagram editor, learns the interfaces described therein, and uses simulation randomization algorithms to drive the interfaces with legal scenarios for the interfaces described in the timing diagram.