Abstract: The present system is employed to generate and transmit information which is needed to construct or assemble truth tables and pertinent data which are directed to associated circuits which require testing. The present method employs a technique whereby information is nested, or compacted, in accordance with certain rules of grammar and is transmitted from a circuit design group to a vendor, i.e., a manufacturer of the circuit designed by a design group. When the nested information is expanded by a translator device, or by a translation program, at the manufactuer's location, it is directly expandable into truth table information for use by various logic testers. Each of the truth tables defines a specific function that the designer wants tested in the associated circuit. The manufacturer supplies the test platform hardware which generates the desired signal patterns defined by the truth table information and pertinent data.