Abstract: Memory systems may include a storage device comprising a first memory; a processor; and a second memory. The memory systems may be configured to read first data from a first storage location of the first memory, store the first data to a first storage location of the second memory and input the first data to a compression block of the storage device, compress the first data and store the compressed first data to a second storage location of the second memory, evaluate the compressed first data, store the first data from the first storage location of the second memory to a different storage location of the first memory when the compressed first data is not deemed compressible, and combine the compressed first data with additional compressed data and store the combined compressed data to a different storage location of the first memory when the compressed first data is deemed compressible.

Abstract: Memory systems may include a storage device comprising a first memory; a processor; and a second memory. The memory systems may be configured to read first data from a first storage location of the first memory, store the first data to a first storage location of the second memory and input the first data to a compression block of the storage device, compress the first data and store the compressed first data to a second storage location of the second memory, evaluate the compressed first data, store the first data from the first storage location of the second memory to a different storage location of the first memory when the compressed first data is not deemed compressible, and combine the compressed first data with additional compressed data and store the combined compressed data to a different storage location of the first memory when the compressed first data is deemed compressible.

Abstract: Methods of operating a storage device include reading first data from a first storage location of a first memory of the storage device, storing the first data to a first storage location of a second memory of the storage device, compressing the first data and storing the compressed first data to a second storage location of the second memory, evaluating the compressed first data to determine if it is deemed compressible, storing the first data from the first storage location of the second memory to a different storage location of the first memory if the compressed first data was determined to not be compressible, and combining the compressed first data with additional compressed data and storing the combined compressed data to a different storage location of the first memory if the compressed first data was determined to be compressible.

Abstract: Methods of operating a storage device include reading first data from a first storage location of a first memory of the storage device, storing the first data to a first storage location of a second memory of the storage device, compressing the first data and storing the compressed first data to a second storage location of the second memory, evaluating the compressed first data to determine if it is deemed compressible, storing the first data from the first storage location of the second memory to a different storage location of the first memory if the compressed first data was determined to not be compressible, and combining the compressed first data with additional compressed data and storing the combined compressed data to a different storage location of the first memory if the compressed first data was determined to be compressible.

Abstract: Methods for programming compressed data to a memory array, memory devices, and memory systems are disclosed. In one such method, memory pages or blocks that are partially programmed with valid data are found. The data is collected from these partially programmed pages or blocks and the data is compressed. The compressed data is then programmed back to different locations in the memory array of the memory device.

Abstract: A master memory controller comprises a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with one or more slave memory controllers. The master and slave memory controllers can operate in a parallel operation mode to communicate with a plurality of memory devices coupled to the memory communication channels of each memory controller.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: A master memory controller comprises a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with one or more slave memory controllers. The master and slave memory controllers can operate in a parallel operation mode to communicate with a plurality of memory devices coupled to the memory communication channels of each memory controller.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: Solid state storage devices and methods for operation of solid state storage devices are disclosed. In one such method, a master memory controller is comprised of a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with one or more slave memory controllers. The master and slave memory controllers can operate in a parallel operation mode to communicate with a plurality of memory devices coupled to the memory communication channels of each memory controller.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: Solid state storage devices and methods for operation of solid state storage devices are disclosed. In one such method, a master memory controller is comprised of a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with one or more slave memory controllers. The master and slave memory controllers can operate in a parallel operation mode to communicate with a plurality of memory devices coupled to the memory communication channels of each memory controller.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: Methods for programming compressed data to a memory array, memory devices, and memory systems are disclosed. In one such method, memory pages or blocks that are partially programmed with valid data are found. The data is collected from these partially programmed pages or blocks and the data is compressed. The compressed data is then programmed back to different locations in the memory array of the memory device.

Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Abstract: An unexpanded perlite ore polishing composition is shown. The composition comprises base material having grains of unexpanded perlite ore of a selected distribution of particle sizes which undergo fracturing of the grains as a function of an abrasive force applied to the base material. The selected distribution of particle sizes includes a significant volume of grains of unexpanded perlite ore having a (d90) particle size in a range of about 101 to about 229 ?m. The base material is responsive to an abrasive force being applied thereto during polishing resulting in continued fracturing of the grains of unexpanded perlite ore to yield a final polishing composition having a sufficiently low level of abrasiveness under said abrasive force making it suitable for use in polishing. Compositions for polishing acrylic dentures and CRT tube surfaces using the unexpanded perlite ore polishing composition and methods for polishing the same are also shown.