Abstract: A ROM shadowing circuit that controls transfer of ROM data to the RAM in order to implement the ROM shadowing process required during the initialization of a PC. When the ROM shadowing circuit detects a system reset signal, the ROM shadowing circuit holds the CPU in a reset state while the ROM shadowing circuit copies the ROM data to the RAM. When the data copy is completed, the ROM shadowing circuit releases the CPU, which then begins fetching and executing instructions that comprise firmware initialization routines from the RAM.

Abstract: A portable computer is described that contains a circuit for receiving pages and performing security functions based on the received page. Once a page has been received by the portable computer, the computer's hard drive can be automatically reformatted, or the portable computer can be prevented from booting. In addition, the portable computer can be programmed to use a modem to automatically dial a security center and transmit security information such as the Caller ID Tag of the current telephone number.

Abstract: An upgradeable cache circuit is described which automatically routes those control signals necessary to maintain cache coherency in a computer system having a processor (with integrated L1 cache) coupled with main memory by a controller. The cache circuit includes an L2 cache module connector and a high speed multiplexer having minimal propagation delay. The multiplexer selects one of two sets of control signals to route to and from the processor, controller and cache circuit, corresponding to the presence or absence of an L2 cache module in the cache module connector.

Abstract: A method for combining a low-speed communications bus and a high-speed communications bus into a single multiplexed communications bus that supports both low-speed and high-speed operations. The multiplexed communications bus contains a low-speed state machine and a high-speed state machine. The multiplexed communications bus is controlled by the low-speed state machine and operated at low speed in order to conduct transactions between two low-speed peripheral devices, and is controlled by the high-speed state machine and operated at high speed in order to conduct transactions between and two high-speed peripheral devices. For transactions between peripheral devices having different speeds, either a buffer is used to store data between data transmission and data reception by the two devices, or the low-speed and high-speed state machines are synchronized and operationally interleaved.

Abstract: A method is described for controlling data transfer operations between a main memory and other devices in a computer system. Data transfer request signals and associated latency identification values are received. Each of the latency identification values corresponds with a maximum time interval in which to service the respective data transfer request. The latency identification values are periodically modified and compared to indicate the current highest priority request. In the event that service of a particular requested data transfer operation must be provided imminently, priority override functionality is provided. In this way, those devices having particular latency requirements can be provided with timely access to the main memory, and need not have separately dedicated memory or buffers.

Abstract: A PCB assembly which allows economical and reliable rework. The PCB assembly contains a soldermask and a trace with a portion of the trace exposed by a soldermask relief When one needs to rework the PCB assembly, one bonds a rework wire, using conventional intermetalic bonding materials, to the portion of the trace exposed by the soldermask relief There is no need to bond a rework wire to a component. Further, there is no need to scrape a off the soldermask and possibly damage the traces and/or vias. The bonds are high reliability bonds, and the labor required to perform such bonds are minimal.

Abstract: A computer system and method is described for improved storage of computer system configuration information. A ROM module includes both a BIOS ROM portion and a configuration ROM portion. The configuration ROM includes a backup copy of the system configuration parameters stored in a battery-powered configuration CMOS RAM. If the configuration CMOS RAM fails to provide valid configuration data, the contents of the configuration ROM are used to configure the computer system. If the contents of the configuration ROM are also invalid, default configuration values are provided by the BIOS ROM. User modification of the default values may be effected through a setup utility program, and the configuration ROM then programmed accordingly.

Abstract: A computer system processes system management interrupt (SMI) requests from plural system management (SM) requesters. Different SM requesters are provided with different priority levels such that high priority system management interrupts can be serviced without waiting for lower priority system management interrupts to be serviced completely. In particular, the system executes a first SMI handler routine in response to receiving a first SMI from a first SM requester. In response to receiving a second SMI asserted by a second SM requester, the system determines whether the second SMI request has been assigned a higher priority than the first SMI request. If so, then the system interrupts executing the first SMI handler routine and executes a second SMI handler routine corresponding to the second SMI request. Otherwise, the system completes executing the first SMI handler routine and then executes the second SMI handler routine.

Abstract: The invention enables reporting of diagnostic data from a user's computer to a diagnostic technician or an automated diagnostic system, and may be advantageously applied to report data over a telephone connection. To facilitate diagnostic data reporting, gathering of diagnostic data is automated and the gathered data is automatically reported using a generated audio signal. Automated reporting using a generated audio signal may be helpful in reducing human errors in the reporting of diagnostic data to remote technicians.

Abstract: An improved biocompatible composition consisting of physiologically-stable, isotropic carbon beads or particles carried in a lubricative suspension, solution, other fluid or gel. The composition is intended to be delivered into the body through a small-bored needle, cannula, or other catheter into a tissue site for the purpose of augmenting the tissue. In particular, the composition is useful for augmenting tissue in the area of the cardiac orifice of the stomach to reduce gastric reflux, in the area of the internal or external sphincter of the anal canal to reduce fecal incontinence or in the area of urethral tissue for the purpose of treating urinary incontinence.

Abstract: An apparatus is described for controlling data transfer operations between a main memory and other devices in a computer system. A memory controller receives data transfer request signals and associated latency identification values, each corresponding with a maximum time interval in which to service the respective data transfer requests. The latency identification values are periodically modified and compared to indicate the current highest priority request. In the event that service of a particular requested data transfer operation must be provided imminently, priority override circuitry is provided. In this way, those devices having particular latency requirements can be provided with timely access to the main memory, and need not have separately dedicated memory or buffers.

Abstract: One embodiment of the present invention provides an apparatus within a computer system that maintains status information for peripheral devices in a status register, which is located within a central processing unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor performs an internal read of the status register to determine which peripheral device requires processing. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention provides an apparatus within a central processing unit that maintains status information for peripheral devices in a status register.

Abstract: Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.

Abstract: A method and system for increasing the rate of data transfer between a PC-based computer and an IDE/ATA-compliant hard drive is disclosed. Synchronous data transfer is employed in a manner that retains full compatibility with the existing IDE/ATA standard.

Abstract: One embodiment of the present invention provides a computer system that maintains status information for several peripheral devices in a status register, which is located within a core logic unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor merely has to read the status register to determine which peripheral device requires processing. This is a very fast operation because the status register is internal to the core logic. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention provides an apparatus within a core logic device that maintains status information for peripheral devices in a status register.

Abstract: One embodiment of the present invention provides an apparatus within a computer system that maintains status information for peripheral devices in a status register, which is located within a central processing unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor performs an internal read of the status register to determine which peripheral device requires processing. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention provides an apparatus within a central processing unit that maintains status information for peripheral devices in a status register.

Abstract: An upgradeable cache circuit is described which automatically routes those control signals necessary to maintain cache coherency in a computer system having a processor (with integrated L1 cache) coupled with main memory by a controller. The cache circuit includes an L2 cache module connector and a high speed multiplexer having minimal propagation delay. The multiplexer selects one of two sets of control signals to route to and from the processor, controller and cache circuit, corresponding to the presence or absence of an L2 cache module in the cache module connector.

Abstract: A power management apparatus includes a power source, a detection circuit to generate a first signal indicating the power transferred to a portion of a computer system from the power source, and a control circuit to generate at least one control signal to effect a power management action based on the first signal. A program storage device (readable by a programmable control device) includes instructions to manage power in a computer system. The program storage device includes instructions to receive a power signal from a power source (the power signal furnishing power to a portion of the computer system), generate a first signal indicating the power transferred from the power source to the portion of the computer system, and generate a second signal to effect a power management action based on the first signal.

Abstract: One embodiment of the present invention provides a computer system that maintains status information for several peripheral devices in a status register, which is located within a core logic unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor merely has to read the status register to determine which peripheral device requires processing. This is a very fast operation because the status register is internal to the core logic. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention provides an apparatus within a core logic device that maintains status information for peripheral devices in a status register.

Abstract: A method that employs a ROM shadowing circuit to transfer ROM data to the RAM in order to implement the ROM shadowing process required during the initialization of a PC. When the ROM shadowing circuit detects a system reset signal, the ROM shadowing circuit holds the CPU in a reset state while the ROM shadowing circuit copies the ROM data to the RAM. When the data copy is completed, the ROM shadowing circuit releases the CPU, which then begins fetching and executing instructions that comprise firmware initialization routines from the RAM.