Patents by Inventor Dean Mulla

Dean Mulla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200110460
    Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
    Type: Application
    Filed: July 16, 2019
    Publication date: April 9, 2020
    Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
  • Patent number: 10365707
    Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 30, 2019
    Assignee: INTEL CORPORATION
    Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
  • Publication number: 20190047579
    Abstract: Methods and apparatus relating to provision of core tightly coupled lockstep for high functional safety are described. In an embodiment, a master core, coupled to a slave core, executes one or more operations to support Advanced Driver Assistance Systems (ADA) or autonomous driving. The master core and the slave core receive the same input signal and core tightly couple logic causes generation of a signal in response to comparison of a first output from the master core and a second output from the slave core. The generated signal causes an interruption of the one or more operations in response to a mismatch between the first output and the second output. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 31, 2018
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: Bahaa Fahim, Riccardo Mariani, Dean Mulla, Robert Gottlieb
  • Publication number: 20180164873
    Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
  • Publication number: 20180164870
    Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
    Type: Application
    Filed: December 8, 2016
    Publication date: June 14, 2018
    Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
  • Patent number: 9910470
    Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Vivek Garg, Alexander Gendler, Arvind Raman, Ashish V. Choubal, Krishnakanth V. Sistla, Dean Mulla, Eric J. Dehaemer, Rahul Agrawal, Guy G. Sotomayor
  • Patent number: 9753525
    Abstract: Systems, methods, and devices are disclosed for mitigating voltage droop in a computing device. An example apparatus includes a plurality of threshold registers to store respective voltage droop thresholds, and an interface to receive a license grant message indicating a license mode for a processor core or domain. The license mode corresponds to a selected set of execution units in the processor core or domain. The apparatus also includes a voltage droop correction module to, based on the license mode indicated in the license grant message, select one of the voltage droop thresholds from the plurality of voltage droop registers, and compare a voltage droop in the processor core or domain with the selected voltage droop threshold. Based on the comparison, the apparatus triggers a voltage droop correction process.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: September 5, 2017
    Assignee: INTEL CORPORATION
    Inventors: Nazar S. Haider, Dean Mulla, Allen W. Chu
  • Patent number: 9720491
    Abstract: Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Dean Mulla, Daniel G. Borkowski, Krishnakanth V. Sistla, Victor Wu, Manev Luthra
  • Patent number: 9710041
    Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Larisa Novakovsky, Krishnakanth V. Sistla, Vivek Garg, Dean Mulla, Ashish V. Choubal, Erik G. Hallnor, Kimberly C. Weier
  • Publication number: 20170177046
    Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Inventors: Vivek Garg, Alexander Gendler, Arvind Raman, Ashish V. Choubal, Krishnakanth V. Sistla, Dean Mulla, Eric J. Dehaemer, Rahul Agrawal, Guy G. Sotomayor
  • Publication number: 20170031412
    Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.
    Type: Application
    Filed: July 29, 2015
    Publication date: February 2, 2017
    Inventors: Alexander Gendler, Larisa Novakovsky, Krishnakanth V. Sistla, Vivek Garg, Dean Mulla, Ashish V. Choubal, Erik G. Hallnor, Kimberly C. Weier
  • Publication number: 20160378173
    Abstract: Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.
    Type: Application
    Filed: June 27, 2015
    Publication date: December 29, 2016
    Applicant: INTEL CORPORATION
    Inventors: Dean Mulla, Daniel G. Borkowski, Krishnakanth V. Sistla, Victor Wu, Manev Luthra
  • Patent number: 9501129
    Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Krishnakanth Sistla, Dean Mulla, Vivek Garg, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa, Jeffrey D. Gilbert
  • Publication number: 20160179163
    Abstract: Systems, methods, and devices are disclosed for mitigating voltage droop in a computing device. An example apparatus includes a plurality of threshold registers to store respective voltage droop thresholds, and an interface to receive a license grant message indicating a license mode for a processor core or domain. The license mode corresponds to a selected set of execution units in the processor core or domain. The apparatus also includes a voltage droop correction module to, based on the license mode indicated in the license grant message, select one of the voltage droop thresholds from the plurality of voltage droop registers, and compare a voltage droop in the processor core or domain with the selected voltage droop threshold. Based on the comparison, the apparatus triggers a voltage droop correction process.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Applicant: Intel Corporation
    Inventors: NAZAR S. HAIDER, DEAN MULLA, ALLEN W. CHU
  • Patent number: 8914650
    Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Krishnakanth Sistla, Dean Mulla, Vivek Garg, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa, Jeffrey D. Gilbert
  • Patent number: 8769295
    Abstract: Embodiments of the invention are generally directed to apparatuses, methods, and systems for a computing system feature activation mechanism. In an embodiment, a computing system receives a remotely generated feature activation information. The computing system compares the remotely generated feature activation information with a built-in feature activation mechanism. In an embodiment, a feature of the computing system is activated if the remotely generated feature activation information matches the built-in feature activation mechanism. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: Dean Mulla, Rahul Khanna, Keith R. Pflederer
  • Publication number: 20130311804
    Abstract: Methods, apparatus, and systems for implementing coordinated idle power management in glueless and clustered systems. Components for facilitating coordination of package idle power state between sockets in a glueless system such as a server platform include a master entity in one socket (i.e., processor) and a slave entity in each socket participating in the power management coordination. Each slave collects idle status inputs from various sources and when the socket cores are sufficiently idle, it makes a request to the master to enter a deeper idle power state. The master coordinates global power management operations in response to the slave requests, including broadcasting a command with a target latency to all of the slaves to allow the processors to enter reduced power (i.e., idle) states in a coordinated manner.
    Type: Application
    Filed: April 30, 2012
    Publication date: November 21, 2013
    Inventors: Vivek Garg, Krishnakanth KK Sistla, Robert Rob Blankenship, Dean Mulla, Daniel Dan Borkowski, Shaun Conrad, Ganapati Gans Srinivasa
  • Publication number: 20130179716
    Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
    Type: Application
    Filed: February 28, 2013
    Publication date: July 11, 2013
    Inventors: Krishnakanth Sistla, Dean Mulla, Vivek Garg, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa, Jeffrey D. Gilbert
  • Publication number: 20130080795
    Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Inventors: Krishnakanth Sistla, Dean Mulla, Vivek Garg, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa, Jeffrey D. Gilbert
  • Patent number: 7376877
    Abstract: A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol different from the first symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: May 20, 2008
    Assignee: Intel Corporation
    Inventors: Nhon Toai Quach, John Fu, Sunny Huang, Jeen Miin, Dean Mulla