Patents by Inventor Dean Tran
Dean Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7610676Abstract: A method for assembling a bundle cable connector assembly that eliminates bird caging, wire threads extruding through a connector pin, loose wire threads, dielectric shield shrinking, etc. The method includes stripping the wire to create a birdcage preventative zone and an exposed tip with a crimping zone therebetween, and tinning the exposed wire at the birdcage preventative zone and the tip. The method then includes inserting the wire into a connector pin, and crimping the pin to the wire at the crimping zone using heat so that the tinning solder melts. The method then includes mounting the pin to a connector body and mounting a wire-locking device to the connector body to lock the pin to the connector body.Type: GrantFiled: February 19, 2007Date of Patent: November 3, 2009Assignee: Northrop Grumman Space & Missions Systems Corp.Inventors: Dean Tran, Alan Hirschberg, Melissa Fuller, Phillip Hayes, Greg Keller
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Patent number: 7476606Abstract: Ultra-high speed semiconductors that are usually very thin and therefore very fragile still require connection to a circuit board and a heat transfer pathway. Ultra-high speed circuits and semiconductor devices are provided with a carrier plate formed on the backside of a wafer or substrate by a variety of deposition methods. The carrier plate is a series of metal layers, each being selected to enable the attachment of a relatively thick copper carrier plate to the backside of the substrate or wafer.Type: GrantFiled: March 28, 2006Date of Patent: January 13, 2009Assignee: Northrop Grumman CorporationInventors: Dean Tran, Alan Hirschberg, Ha K. DeMarco, Luis Rochin, Thomas Chung, Mark Kintis, Steven J. Mass
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Publication number: 20080196246Abstract: A method for assembling a bundle cable connector assembly that eliminates bird caging, wire threads extruding through a connector pin, loose wire threads, dielectric shield shrinking, etc. The method includes stripping the wire to create a birdcage preventative zone and an exposed tip with a crimping zone therebetween, and tinning the exposed wire at the birdcage preventative zone and the tip. The method then includes inserting the wire into a connector pin, and crimping the pin to the wire at the crimping zone using heat so that the tinning solder melts. The method then includes mounting the pin to a connector body and mounting a wire-locking device to the connector body to lock the pin to the connector body.Type: ApplicationFiled: February 19, 2007Publication date: August 21, 2008Applicant: Northrop Grumman Space & Missions Systems Corp.Inventors: Dean Tran, Alan Hirschberg, Melissa Fuller, Phillip Hayes, Greg Keller
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Patent number: 7315069Abstract: An integrated getter structure and a method for its formation and installation in a circuit module enclosure (24). The integrated structure includes a hydrogen getter structure (10) and selected quantities of a material (20) that is formulated to provide both a particle getter function and an RF absorber function. In one embodiment, the material (20) is placed in discrete quantities over the hydrogen getter structure (10). In another embodiment, the hydrogen getter structure (10) is formed over a sheet of the material (20) and is provided with apertures (30) to expose the material (20).Type: GrantFiled: November 24, 2004Date of Patent: January 1, 2008Assignee: Northrop Grumman CorporationInventors: Dean Tran, Jerry T. Fang, Yoshio Saito, Mark Kintis, Chih Chang, Phu H. Tran
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Publication number: 20070235744Abstract: Ultra-high speed semiconductors that are usually very thin and therefore very fragile still require connection to a circuit board and a heat transfer pathway. Ultra-high speed circuits and semiconductor devices are provided with a carrier plate formed on the backside of a wafer or substrate by a variety of deposition methods. The carrier plate is a series of metal layers, each being selected to enable the attachment of a relatively thick copper carrier plate to the backside of the substrate or wafer.Type: ApplicationFiled: March 28, 2006Publication date: October 11, 2007Inventors: Dean Tran, Alan Hirschberg, Ha DeMarco, Luis Rochin, Thomas Chung, Mark Kintis, Steven Mass
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Publication number: 20070184285Abstract: Protection against x-ray radiation is provided by a thin layer of a zinc-based alloy. An electronics component housing and lid are made to include a base of a lightweight alloy, a thin coating of the zinc-based alloy and an exterior finish metal layer. The zinc-based alloy provides excellent radiation protection and other advantages, without a significant weight penalty.Type: ApplicationFiled: February 8, 2006Publication date: August 9, 2007Inventors: Dean Tran, Thomas Chung, Alan Hirschberg, Luis Rochin, Mark Kintis
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Publication number: 20060110299Abstract: An integrated getter structure and a method for its formation and installation in a circuit module enclosure (24). The integrated structure includes a hydrogen getter structure (10) and selected quantities of a material (20) that is formulated to provide both a particle getter function and an RF absorber function. In one embodiment, the material (20) is placed in discrete quantities over the hydrogen getter structure (10). In another embodiment, the hydrogen getter structure (10) is formed over a sheet of the material (20) and is provided with apertures (30) to expose the material (20).Type: ApplicationFiled: November 24, 2004Publication date: May 25, 2006Inventors: Dean Tran, Jerry Fang, Yoshio Saito, Mark Kintis, Chih Chang, Phu Tran
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Patent number: 7012943Abstract: A device and a process for integrating light energy transmit and/or receive functions with active devices such as GaAs or InP devices or light emitting devices, such as lasers. The device and process includes forming a passivation layer on top of the active device and forming a silicon photodetector on top of the passivation layer. The photodetector may be formed utilizing a standard solar cell growth process and may be formed as a mesa on top of the active or light-emitting device, thus forming a relatively less complicated semiconductor with an integrated monitoring device.Type: GrantFiled: June 28, 2001Date of Patent: March 14, 2006Assignee: Northrop Grumman CorporationInventors: Dean Tran, Eric R. Anderson, George J. Vendura, Jr.
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Patent number: 6965714Abstract: The invention relates to an optical, integrated alignment device for accurately aligning and efficiently coupling energy between in-plane optical devices. A semiconductor substrate is etched to include a groove for an optical fiber and a lens for passing an optical signal from a cut fiber to a photodetector. The etched semiconductor substrate may be used to pass an optical signal from a surface light emitting device to a cut fiber. The end of the optical fiber is cut at a slant that redirects an optical signal from the fiber through the lens or vice-versa. The lens focuses the optical signal onto a target.Type: GrantFiled: June 13, 2002Date of Patent: November 15, 2005Assignee: Northrop Grumman CorporationInventors: John C. Brock, Dean Tran, Edward A. Rezek, Christian L. Marquez, Michelle M. Hazard
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Patent number: 6945447Abstract: A chip or die attachment process and related apparatus, in which a desired quantity of solder (7 or 17) is dispensed onto each, in turn, of a number of desired locations on a substrate (4 or 18), and then an integrated-circuit chip (10) is precisely positioned at each location immediately after the solder is dispensed at that location. Hot gas heaters are used both to heat the solder (7 or 17) as it is dispensed onto the substrate (4 or 18), and to heat the integrated-circuit chip (10) and to reflow the solder beneath the chip. In one form of the invention, the solder is dispensed from a wire spool (1) and melted in position on the substrate (4). Alternatively, the solder is dispensed as a drop (16) from a liquid solder reservoir (13).Type: GrantFiled: June 5, 2002Date of Patent: September 20, 2005Assignee: Northrop Grumman CorporationInventors: Dean Tran, Salim Akbany, Maurice Lowery, Leon M. Singleton, Jr., Ronald A. DePace
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Patent number: 6805786Abstract: A relatively simple and inexpensive process for plating precious alloyed metals, such as AuSn, AuSnIn, AgSn, AuIn and AgIn. Anodes are formed from each of the metal components in the alloy and disposed in a conducting solution. The mass of each metal components is determined by Faraday's law. The target is also disposed in the conducting solution. Plating current is independently applied to each anode. The plating is conducted under an ultraviolet light sources to optimize the process. The plating alloys can be used for various purposes including attaching a semiconductor die to a substrate. Since the process does not involve exposure of the semiconductor die to a relatively high temperature for a relatively long time, the process does not pose a risk of contamination of the semiconductor by the adhesive or wax used to hold the die in place on the carrier during processing.Type: GrantFiled: September 24, 2002Date of Patent: October 19, 2004Assignee: Northrop Grumman CorporationInventors: Dean Tran, Salim Akbany, Ronald A. DePace, William L. Jones, Roosevelt Johnson
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Patent number: 6786652Abstract: A process for fabricating a photonics package includes securing a ferrule to an optical fiber, inserting the ferrule through a movable flange into a photonics housing containing a photodiode, adjusting the ferrule longitudinally within the flange to position the end of the optical fiber with respect to the surface of the photodiode and welding the ferrule to the flange. Thereafter, the ferrule and flange assembly is adjusted laterally with respect to the photodiode and the lower end of the flange is secured to the housing using hot gas injection or laser soldering which allows lateral adjustment of the fiber during the solder cooling process for final positioning with respect to the photodiode.Type: GrantFiled: December 19, 2001Date of Patent: September 7, 2004Assignee: Northrop Grumman CorporationInventors: Christian L. Marquez, James A. Hathaway, Michelle M. Hazard, Dean Tran
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Publication number: 20040055889Abstract: A relatively simple and inexpensive process for plating precious alloyed metals, such as AuSn, AuSnIn, AgSn, AuIn and AgIn. Anodes are formed from each of the metal components in the alloy and disposed in a conducting solution. The mass of each metal components is determined by Faraday's law. The target is also disposed in the conducting solution. Plating current is independently applied to each anode. The plating is conducted under an ultraviolet light sources to optimize the process. The plating alloys can be used for various purposes including attaching a semiconductor die to a substrate. Since the process does not involve exposure of the semiconductor die to a relatively high temperature for a relatively long time, the process does not pose a risk of contamination of the semiconductor by the adhesive or wax used to hold the die in place on the carrier during processing.Type: ApplicationFiled: September 24, 2002Publication date: March 25, 2004Inventors: Dean Tran, Salim Akbany, Ronald A. DePace, William L. Jones, Roosevelt Johnson
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Publication number: 20030231828Abstract: The invention relates to an optical, integrated alignment device for accurately aligning and efficiently coupling energy between in-plane optical devices. A semiconductor substrate is etched to include a groove for an optical fiber and a lens for passing an optical signal from a cut fiber to a photodetector. The etched semiconductor substrate may be used to pass an optical signal from a surface light emitting device to a cut fiber. The end of the optical fiber is cut at a slant that redirects an optical signal from the fiber through the lens or vice-versa. The lens focuses the optical signal onto a target.Type: ApplicationFiled: June 13, 2002Publication date: December 18, 2003Inventors: John C. Brock, Dean Tran, Edward A. Rezek, Christian L. Marquez, Michelle M. Hazard
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Publication number: 20030226877Abstract: A chip or die attachment process and related apparatus, in which a desired quantity of solder (7 or 17) is dispensed onto each, in turn, of a number of desired locations on a substrate (4 or 18), and then an integrated-circuit chip (10) is precisely positioned at each location immediately after the solder is dispensed at that location. Hot gas heaters are used both to heat the solder (7 or 17) as it is dispensed onto the substrate (4 or 18), and to heat the integrated-circuit chip (10) and to reflow the solder beneath the chip. In one form of the invention, the solder is dispensed from a wire spool (1) and melted in position on the substrate (4). Alternatively, the solder is dispensed as a drop (16) from a liquid solder reservoir (13).Type: ApplicationFiled: June 5, 2002Publication date: December 11, 2003Inventors: Dean Tran, Salim Akbany, Maurice Lowery, Leon M. Singleton, Ronald A. DePace
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Patent number: 6613600Abstract: A resonant photodetector assembly (10) which uses multiple reflections of light within a photodetector (20) to convert input light into an electrical signal. The photodetector (20) includes a combination of generally planar semiconductor layers including a photodetector active layer (36) where light is converted into an electrical output. The photodetector (20) further includes a first outer electrical contact layer (34) and a second outer electrical contact layer (42). A waveguide (22) is positioned on the photodetector (20) and has a waveguide active layer (26) positioned between a pair of waveguide cladding layers (24, 28), a first end (30) for receiving input light and a second end (50) for reflecting the light. A reflector (32) is positioned on the second end (50) of the waveguide (22) at an angle relative to a line parallel to the substrate (14), where the reflector (32) reflects the light received by the first end (30) of the waveguide active layer (26) towards the photodetector (20).Type: GrantFiled: October 24, 2001Date of Patent: September 2, 2003Assignee: TRW Inc.Inventors: Dean Tran, Edward A. Rezek, Eric R. Anderson, William L. Jones
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Publication number: 20030113075Abstract: A process for fabricating a photonics package includes securing a ferrule to an optical fiber, inserting the ferrule through a movable flange into a photonics housing containing a photodiode, adjusting the ferrule longitudinally within the flange to position the end of the optical fiber with respect to the surface of the photodiode and welding the ferrule to the flange. Thereafter, the ferrule and flange assembly is adjusted laterally with respect to the photodiode and the lower end of the flange is secured to the housing using hot gas injection or laser soldering which allows lateral adjustment of the fiber during the solder cooling process for final positioning with respect to the photodiode.Type: ApplicationFiled: December 19, 2001Publication date: June 19, 2003Inventors: Christian L. Marquez, James A. Hathaway, Michelle M. Hazard, Dean Tran
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Publication number: 20030091296Abstract: A cold welding technique for securing a fiber optic cable (10) to a ferrule (26). The fiber optic cable (10) is inserted into a sleeve (12). The fiber cable and sleeve assembly is then slid into a sleeve bore (24) through one end of the ferrule (26) so that the fiber (14) extends out of an opposite end (40) of the ferrule (26). The sleeve (12) is then retracted from the ferrule (26). A cold electroplating process is performed so that a layer (50) of a suitable plating material is deposited over the end (40) of the ferrule (26) through which the fiber (14) extends so that the fiber cable (10) is held within the ferrule (26) and the ferrule opening is hermetically sealed. The sleeve (12) is then slid back into the ferrule (26) and is soldered to a fiber jacket (10) of the cable (10) to hold it in the desired location.Type: ApplicationFiled: November 14, 2001Publication date: May 15, 2003Inventors: Dean Tran, Jack S. McLaren, David M. Hernandez, Michelle M. Hazard, Sonny D. Le, Christian L. Marquez
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Patent number: 6558047Abstract: A cold welding technique for securing a fiber optic cable (10) to a ferrule (26). The fiber optic cable (10) is inserted into a sleeve (12). The fiber cable and sleeve assembly is then slid into a sleeve bore (24) through one end of the ferrule (26) so that the fiber (14) extends out of an opposite end (40) of the ferrule (26). The sleeve (12) is then retracted from the ferrule (26). A cold electroplating process is performed so that a layer (50) of a suitable plating material is deposited over the end (40) of the ferrule (26) through which the fiber (14) extends so that the fiber cable (10) is held within the ferrule (26) and the ferrule opening is hermetically sealed. The sleeve (12) is then slid back into the ferrule (26) and is soldered to the ferrule to hold it in the desired location.Type: GrantFiled: November 14, 2001Date of Patent: May 6, 2003Assignee: Northrop Grumman CorporationInventors: Dean Tran, Jack S. McLaren, David M. Hernandez, Michelle M. Hazard, Sonny D. Le, Christian L. Marquez
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Publication number: 20030002555Abstract: A device and a process for integrating light energy transmit and/or receive functions with active devices such as GaAs or InP devices or light emitting devices, such as lasers. The device and process includes forming a passivation layer on top of the active device and forming a silicon photodetector on top of the passivation layer. The photodetector may be formed utilizing a standard solar cell growth process and may be formed as a mesa on top of the active or light-emitting device, thus forming a relatively less complicated semiconductor with an integrated monitoring device.Type: ApplicationFiled: June 28, 2001Publication date: January 2, 2003Inventors: Dean Tran, Eric R. Anderson, George J. Vendura