Patents by Inventor Dean Wang

Dean Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250069926
    Abstract: Integrated substrate processing systems are disclosed that are able to achieve high-volume processing of substrates (e.g., greater than 120 substrates per hour) using environmentally sensitive processes and/or tools, such as photolithography processes and/or tools. In some embodiments, for example, the integrated substrate processing system may include an EFEM and a processing tool enclosure that are coupled together to form an integrated processing environment. The integrated substrate processing system may operate to maintain substantially uniform conditions (e.g., at a uniform temperature and relative humidity) throughout the integrated environment, and in some embodiments, may utilize an external air source, such as a remote air module (RAM), in order to do so. In some embodiments, high-volume processing of substrates may be further facilitated by employing specialized substrate handling robots and/or specially adapting the EFEM and/or processing tool enclosure.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 27, 2025
    Inventors: Arunkumar Ramachandraiah, Paul Reuter, Devendra Holeyannavar, Steven Trey Tindel, Dean Hruzek, Jeffrey Hudgens, Maureen Breiling, Venkatesh Chinnaplar Rajappa, Micah E. Klaeser, Benjamin Johnston, Alton Wang, Wei Siang Chao, Chandrakant Sapkale, Shiva Prasad Kota, Latha Ramesh
  • Patent number: 12237615
    Abstract: A floating quad connector assembly is designed to hold two pairs of simplex connecters in a quad formation and to permit the two pairs of connectors to float within the assembly, thereby rendering the quad connector assembly compatible with different quad adapters having different spacings between the two middle simplex ports. Also, a segmental switch module is configured to aggregate multiple category-rated connectors in an array formation while permitting the spacings between the connectors to float, thereby rendering the switch module compatible with port arrays of different port-to-port spacings.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: February 25, 2025
    Assignee: LEVITON MANUFACTURING CO., INC.
    Inventors: Dean Lipke, Daniel Underbrink, Hua Wang
  • Publication number: 20250063289
    Abstract: This application relates to earbuds configured with one or more biometric sensors. At least one of the biometric sensors is configured to be pressed up against a portion of the tragus for making biometric measurements. In some embodiments, the housing of the earbud can be symmetric so that the earbud can be worn interchangeably in either a left or a right ear of a user. In such an embodiment, the earbud can include a sensor and circuitry configured to determine and alter operation of the earbud in accordance to which ear the earbud is determined to be sitting in.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Applicant: APPLE INC.
    Inventors: Phillip Qian, Edward Siahaan, Erik L. Wang, Christopher J. Stringer, Matthew Dean Rohrbach, Daniel Max Strongwater, Jason J. LeBlanc
  • Publication number: 20250030110
    Abstract: A traction battery includes a battery array and a flexible printed circuit (FPC). The FPC including a hurdle-shaped flexible substrate that is planar and has opposing first and second planar surfaces and opposing first and second edges extending between the planar surfaces, the substrate having a straight middle portion, a first end portion that is joined to the middle portion by a first elbow portion, and a second end portion that is joined to the middle portion by a second elbow portion. The elbow portions are folded relative to the middle portion at first and second folds, respectively, such that the first planar surfaces of the first and second elbows face each other. A circuit is supported by the substrate and electrically connected between circuit boards supported on opposite sides of the battery array.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 23, 2025
    Inventors: Youngcai WANG, Brian UTLEY, Chi PAIK, Dean Joseph DEANGELIS, Mark PARENTI, Francisco FERNANDEZ-GALINDO
  • Patent number: 12151628
    Abstract: Particular embodiments described herein provide for a system and method to help prevent condensation inside an enclosure that includes an electronic system. The system and method can determine a current relative humidity of an environment inside an enclosure that houses the electronic system, use the current relative humidity and the current maximum temperature to determine a dew point for the environment inside the enclosure, activate one or more heating elements inside the enclosure when the current minimum temperature is the same or lower than the dew point for the environment inside the enclosure, activate one or more embedded fans, and open one or more vents to help purge moisture out of the system during heating. When the current minimum temperature is higher than the dew point for the environment inside the enclosure, the system and method can allow the electronic system to power on.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: November 26, 2024
    Assignee: GM Cruise Holdings LLC
    Inventors: Fen Chen, Gilberto Madrid Gomez, Tyler Sawyer, Dean Wang, Arul Ramalingam, Timothy Seto
  • Publication number: 20240153457
    Abstract: The present invention is related to a display device, including: a plurality of sub-pixel areas, each including a pixel circuit, each pixel circuit including: a diode, configured to be in a forward-biasing state during a display phase of the pixel circuit for light-emitting and configured to be in a reverse-biasing state in a sensing phase of the pixel circuit for light-sensing; a driving transistor for driving the diode during the display phase and serving as a source follower in the sensing phase; first to sixth transistors, applied to the gates of the first to sixth transistors respectively so that the pixel circuit switching between the display phase and the sensing phase; and a capacitor for storing a data voltage to be written to the diode in the display phase and storing the charge accumulated by the diode in the sensing phase.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 9, 2024
    Inventors: Ping-Hung Yin, Jia-Shyang Wang, Dean Wang
  • Publication number: 20240042953
    Abstract: Particular embodiments described herein provide for a system and method to help prevent condensation inside an enclosure that includes an electronic system. The system and method can determine a current relative humidity of an environment inside an enclosure that houses the electronic system, use the current relative humidity and the current maximum temperature to determine a dew point for the environment inside the enclosure, activate one or more heating elements inside the enclosure when the current minimum temperature is the same or lower than the dew point for the environment inside the enclosure, activate one or more embedded fans, and open one or more vents to help purge moisture out of the system during heating. When the current minimum temperature is higher than the dew point for the environment inside the enclosure, the system and method can allow the electronic system to power on.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: GM Cruise Holdings LLC
    Inventors: Fen Chen, Gilberto Madrid Gomez, Tyler Sawyer, Dean Wang, Arul Ramalingam, Timothy Seto
  • Publication number: 20230388668
    Abstract: Provided is an image sensor circuit, including a pixel array and a plurality of different control circuits. The pixel array comprises a plurality of pixel circuit groups arranged in an array. Each pixel circuit group comprises a plurality of pixel circuits that generate corresponding sensitivity values over exposure duration. The pixel circuits include a first quantity of first pixel circuits, and a second quantity of second pixel circuits. The plurality of different control circuits are respectively coupled to different pixel circuits to control the exposure duration thereof with different transmission signals. The different control circuits are also set to control different pixel circuits to output photo-sensed values at different frame rates. The image sensor circuit periodically generates the pixel value of each pixel circuit group according to first and second exposure durations, first and second frame rates, and first and second light sensitivity values of each pixel circuit group.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 30, 2023
    Inventors: Ping-Hung Yin, Jia-Shyang Wang, Dean Wang
  • Publication number: 20230388610
    Abstract: The present invention relates to an image sensing device comprising: an image sensing array and an image processing circuit. The image sensing array includes sub-array regions used to obtain sensing signals having different exposure period, wherein in a main frame period, the sensing signals include static sensing signals and dynamic sensing signals, the number of the static sensing signals and the dynamic sensing signals are any different positive integers, the static sensing signals are generated at a first frame rate for a first exposure period, and the dynamic sensing signal are generated at a second frame rate for a second exposure period. The image processing circuit analyzes the static sensing signals and the dynamic sensing signals, outputs sub-frames of the sensing signals having the same frame rate in the sub-array region, and fuses the sub-frames each having a different frame rate by a specific ratio to generate a main frame.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 30, 2023
    Inventors: Ping-Hung Yin, Jia-Shyang Wang, Dean Wang
  • Publication number: 20230370749
    Abstract: An image sensor and an image sensing method are provided. A readout circuit outputs a first digital sensing signal according to a floating diffusion node voltage of a first pixel circuit reset after a reset stage and a floating diffusion node voltage of a second pixel circuit reset after the reset stage during a reset signal readout period. The readout circuit outputs a second digital sensing signal according to a sensing result of the first pixel circuit and the floating diffusion node voltage of the second pixel circuit reset after the same reset stage during a sensing signal readout period. The image processing circuit judges whether a digital number of at least one of the first digital sensing signal and the second digital sensing signal is abnormal to decide to keep an original digital number, directly set a pixel value, or reset the second digital sensing signal.
    Type: Application
    Filed: April 19, 2023
    Publication date: November 16, 2023
    Applicant: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
    Inventors: Ping-Hung Yin, Jia-Shyang Wang, Dean Wang
  • Publication number: 20230370743
    Abstract: An image sensor and an image sensing method are provided. The image sensor includes a first pixel circuit, a second pixel circuit, a ramp signal generating circuit, a comparator, and a signal processing circuit. The first pixel circuit has a first floating diffusion node. The second pixel circuit has a second floating diffusion node. The ramp signal generating circuit respectively provides a first ramp signal and a second ramp signal to the first floating diffusion node and the second floating diffusion node during a dark sun detection period. The comparator receives a first node voltage of the first floating diffusion node and a second node voltage of the second floating diffusion node. The signal processing circuit determines whether to output an output signal and determines whether to overwrite a digital value corresponding to a sensing signal according to whether the comparator is triggered.
    Type: Application
    Filed: April 19, 2023
    Publication date: November 16, 2023
    Applicant: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
    Inventors: Ping-Hung Yin, Jia-Shyang Wang, Dean Wang
  • Patent number: 11121261
    Abstract: A semiconductor substrate includes a substrate, a first metal oxide semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a second metal oxide semiconductor layer. The first transistor includes a first metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a first gate of the first conductive layer, a first source of the second conductive layer, and a first drain of the second conductive layer. The second transistor includes a second metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a second gate of the first conductive layer, a second source of the second conductive layer, a second drain of the second conductive layer, and a third metal oxide semiconductor pattern of the second metal oxide semiconductor layer.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: September 14, 2021
    Assignee: Au Optronics Corporation
    Inventors: Wei-Ting Lin, Dean Wang, Chun-Cheng Cheng
  • Publication number: 20210005750
    Abstract: A semiconductor substrate includes a substrate, a first metal oxide semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a second metal oxide semiconductor layer. The first transistor includes a first metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a first gate of the first conductive layer, a first source of the second conductive layer, and a first drain of the second conductive layer. The second transistor includes a second metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a second gate of the first conductive layer, a second source of the second conductive layer, a second drain of the second conductive layer, and a third metal oxide semiconductor pattern of the second metal oxide semiconductor layer.
    Type: Application
    Filed: February 5, 2020
    Publication date: January 7, 2021
    Applicant: Au Optronics Corporation
    Inventors: Wei-Ting Lin, Dean Wang, Chun-Cheng Cheng
  • Patent number: 10807957
    Abstract: A tetradentate chelating monoquinoline derivative with a structure as shown in formula (I) is able to specifically chelate redox active metal ions like copper ions that are dis-regulated in neurodegenerative diseases (Alzheimer's disease, Huntington's disease, Parkinson's disease, and amyotrophic lateral sclerosis), or copper accumulation disease like Wilson's disease. The binding constants of these derivatives for zinc are 6-10 orders of magnitude below that ones for copper, and these derivatives have a good capability of reducing an oxidative stress. The method for preparing the derivative is simple and the derivatives have good application prospects in manufacturing drugs for neurodegenerative diseases and diseases related to disorder of copper metabolism.
    Type: Grant
    Filed: November 24, 2018
    Date of Patent: October 20, 2020
    Inventors: Yan Liu, Xingguo Liu, Weixin Zhang, Daya Huang, Meijie Huang, Dean Wang, Ju Huang, Siwei Shu, Michel Nguyen, Anne Robert, Bernard Meunier
  • Publication number: 20190092730
    Abstract: A tetradentate chelating monoquinoline derivative with a structure as shown in formula (I) is able to specifically chelate redox active metal ions like copper ions that are dis-regulated in neurodegenerative diseases (Alzheimer's disease, Huntington's disease, Parkinson's disease, and amyotrophic lateral sclerosis), or copper accumulation disease like Wilson's disease. The binding constants of these derivatives for zinc are 6-10 orders of magnitude below that ones for copper, and these derivatives have a good capability of reducing an oxidative stress. The method for preparing the derivative is simple and the derivatives have good application prospects in manufacturing drugs for neurodegenerative diseases and diseases related to disorder of copper metabolism.
    Type: Application
    Filed: November 24, 2018
    Publication date: March 28, 2019
    Inventors: Yan LIU, Xingguo LIU, Weixin ZHANG, Daya HUANG, Meijie HUANG, Dean WANG, Ju HUANG, Siwei SHU, Michel NGUTEN, Anne ROBERT, Bernard MEUNIER
  • Patent number: 9984999
    Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Lee, Dean Wang, Mirng-Ji Lii, Chen-Hua Yu
  • Patent number: 9659918
    Abstract: A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Dean Wang, Chen-Shien Chen, Chung-Shi Liu, Jiun Yi Wu
  • Publication number: 20160247786
    Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.
    Type: Application
    Filed: May 5, 2016
    Publication date: August 25, 2016
    Inventors: Chien-Hsun Lee, Dean Wang, Mirng-Ji Lii, Chen-Hua Yu
  • Publication number: 20160163683
    Abstract: A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 9, 2016
    Inventors: Chen-Hua Yu, Dean Wang, Chen-Shien Chen, Chung-Shi Liu, Jiun Yi Wu
  • Publication number: 20150137328
    Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.
    Type: Application
    Filed: January 13, 2015
    Publication date: May 21, 2015
    Inventors: Dean Wang, Chen-Shien Chen, Kai-Ming Ching, Bo-I Lee, Chien-Hsiun Lee