Abstract: A low power signal detector circuit in which a first current limiting device supplies current or draws currents to maintain the voltage across an integrating capacitance to a selected value. A second and variable current limiting means responsive to the RF input signal amplitude is coupled to a common junction of the integrating capacitance and the first current limiting device so as to oppositely affect the charge on the capacitance as provided by the first current limiting device dependent upon the input signal value with respect to a preselected input signal voltage threshold amplitude. The first current limiting device and the variable current limiting device are conveniently implemented using metal-oxide-semiconductor-field-effect transistors operated in the weak-inversion mode so as to maintain power consumption at a minimum.