Patents by Inventor Deanna P. Dunn
Deanna P. Dunn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8250305Abstract: Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.Type: GrantFiled: March 19, 2008Date of Patent: August 21, 2012Assignee: International Business Machines CorporationInventors: Gary E. Strait, Deanna P. Dunn, Michael F. Fee, Pak-kin Mak, Robert J. Sonnelitter, III
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Publication number: 20110258394Abstract: A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining that the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data.Type: ApplicationFiled: June 30, 2011Publication date: October 20, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deanna P. Dunn, Robert J. Sonnelitter, III, Gary E. Strait
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Patent number: 8006039Abstract: A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining if the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data. A corresponding system and computer program product.Type: GrantFiled: February 25, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Deanna P. Dunn, Robert J. Sonnelitter, III, Gary E. Strait
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Patent number: 7779189Abstract: A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.Type: GrantFiled: February 21, 2008Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Deanna P. Dunn, Garrett M. Drapala, Michael F. Fee, Pak-kin Mak, Craig R. Walters
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Publication number: 20090240891Abstract: Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary E. Strait, Deanna P. Dunn, Michael F. Fee, Pak-kin Mak, Robert J. Sonnelitter, III
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Publication number: 20090216933Abstract: A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.Type: ApplicationFiled: February 21, 2008Publication date: August 27, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deanna P. Dunn, Garrett M. Drapala, Michael F. Fee, Pak-kin Mak, Craig R. Walters
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Publication number: 20090216915Abstract: A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining if the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data. A corresponding system and computer program product.Type: ApplicationFiled: February 25, 2008Publication date: August 27, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deanna P. Dunn, Robert J. Sonnelitter, III, Gary E. Strait
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Patent number: 7574548Abstract: As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there is an ongoing half-speed transfer. If there is an ongoing low speed transfer, the system dynamically time shift or slows down the read rate out of the interleave buffer to half speed, and utilizes the free half of the bandwidth. This dynamic “zippering” or time shifting of data prevents a pipe pass from being rejected because the whole data bus is unavailable.Type: GrantFiled: September 12, 2007Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Garrett M. Drapala, Deanna P. Dunn, Michael Fee
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Publication number: 20090070498Abstract: As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there is an ongoing half-speed transfer. If there is an ongoing low speed transfer, the system dynamically time shift or slows down the read rate out of the interleave buffer to half speed, and utilizes the free half of the bandwidth. This dynamic “zippering” or time shifting of data prevents a pipe pass from being rejected because the whole data bus is unavailable.Type: ApplicationFiled: September 12, 2007Publication date: March 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Garrett M. Drapala, Deanna P. Dunn, Michael Fee
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Publication number: 20090006693Abstract: A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.Type: ApplicationFiled: June 27, 2007Publication date: January 1, 2009Applicant: International Business Machiness CorporationInventors: Deanna P. Dunn, Christine C. Jones, Arthur J. O'Neill, Vesselina K. Papazova, Robert J. Sonnelitter, III, Craig R. Walters