Abstract: A system, power management system and method are disclosed. The power management system includes a pitot tube, one or more heating elements disposed in the pitot tube, and one or more power switches, wherein each power switch of the one or more power switches is coupled to a respective heating element and configured to energize or de-energize the respective heating element in response to a control signal. The power management system also includes a temperature detector coupled to the pitot tube and configured to determine a temperature of the pitot tube, and a processor complex coupled to the one or more power switches and the temperature detector and configured to output the control signal to energize or de-energize at least one of the heating elements through a respective at least one of the respective one or more power switches in response to at least the determined temperature of the pitot tube or a detection of a fault.

Abstract: Apparatuses and methods for configuration and operation of data communication connectors supporting connectivity to various physical interfaces are provided.

Abstract: Apparatuses and methods for configuration and operation of data communication connectors supporting connectivity to various physical interfaces are provided.

Abstract: A system, power management system and method are disclosed. The power management system includes a pitot tube, one or more heating elements disposed in the pitot tube, and one or more power switches, wherein each power switch of the one or more power switches is coupled to a respective heating element and configured to energize or de-energize the respective heating element in response to a control signal. The power management system also includes a temperature detector coupled to the pitot tube and configured to determine a temperature of the pitot tube, and a processor complex coupled to the one or more power switches and the temperature detector and configured to output the control signal to energize or de-energize at least one of the heating elements through a respective at least one of the respective one or more power switches in response to at least the determined temperature of the pitot tube or a detection of a fault.

Abstract: Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.

Abstract: A clamp-point active circuit is provided. The clamp-point active circuit includes a rate amplifier configured to receive an output from a device transitioning between at least two levels. The clamp-point active circuit has at least one switching device configured to receive an output from the rate amplifier. The at least one switching device is in at least one respective feedback loop of the rate amplifier. A switching of the at least one switching device causes the rate amplifier to amplify with high linearity in a desired operating range and to clamp outputs received from the transitioning device that are outside the desired operating range to a fixed level.

Abstract: Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.

Abstract: Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.

Abstract: A clamp-point active circuit is provided. The clamp-point active circuit includes a rate amplifier configured to receive an output from a device transitioning between at least two levels. The clamp-point active circuit has at least one switching device configured to receive an output from the rate amplifier. The at least one switching device is in at least one respective feedback loop of the rate amplifier. A switching of the at least one switching device causes the rate amplifier to amplify with high linearity in a desired operating range and to clamp outputs received from the transitioning device that are outside the desired operating range to a fixed level.

Abstract: Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.

Abstract: Electronic circuit breakers and systems for isolating a load from a power-supply unit are provided. One electronic circuit breaker includes a current sensor, a switching element coupled to the current sensor, and a switch controller coupled to the current sensor and the switching element. The switch controller is powered by the power-supply unit and is configured to switch OFF the switching element when the current sensor detects an amount of current from the power-supply unit greater than a predetermined amount. An electronic system includes a power-supply unit, a load, and the above-referenced electronic circuit breaker coupled to the power-supply unit and the load.

Abstract: Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.

Abstract: Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.

Abstract: Electronic circuit breakers and systems for isolating a load from a power-supply unit are provided. One electronic circuit breaker includes a current sensor, a switching element coupled to the current sensor, and a switch controller coupled to the current sensor and the switching element. The switch controller is powered by the power-supply unit and is configured to switch OFF the switching element when the current sensor detects an amount of current from the power-supply unit greater than a predetermined amount. An electronic system includes a power-supply unit, a load, and the above-referenced electronic circuit breaker coupled to the power-supply unit and the load.

Abstract: Systems and methods for current management for digital logic devices are provided. In one embodiment, a method of current management for a digital logic circuit comprises drawing power to drive a digital logic integrated circuit; determining a priori information about an impending current need of the digital logic integrated circuit; and controlling a bypass current in parallel with the digital logic integrated circuit based on the a priori information, wherein the bypass current is controlled to reduce discontinuities in the current supplied by a power supply.

Abstract: Systems and methods for Current Management of Digital Logic Devices are provided. In one embodiment a method for calibrating a digital logic circuit current management system is provided. The method comprises activating one or more synchronous logic paths of a plurality of synchronous logic paths within the digital logic integrated circuit; sampling a voltage powering the digital logic integrated circuit while activating the one or more synchronous logic paths; storing one or more data samples representative of the sampled voltage; and calculating a bypass current setpoint based on the one or more data samples, wherein the bypass current setpoint specifies one or more bypass current characteristic to prevent the voltage powering the digital logic integrated circuit from dropping below a reference voltage.

Abstract: Systems and methods for Current Management of Digital Logic Devices is provided. In one embodiment, a method of current management for a digital logic circuit is provided. The method comprises drawing power to drive a digital logic integrated circuit; performing one or more switching operations with the digital logic integrated circuit; learning at least one bypass current setpoint based on a voltage powering the digital logic integrated circuit while performing the one or more switching operations.

Abstract: Systems and methods for current management for digital logic devices are provided. In one embodiment, a method of current management for a digital logic circuit comprises drawing power to drive a digital logic integrated circuit; determining a priori information about an impending current need of the digital logic integrated circuit; and controlling a bypass current in parallel with the digital logic integrated circuit based on the a priori information, wherein the bypass current is controlled to reduce discontinuities in the current supplied by a power supply.

Abstract: Systems and methods for Current Management of Digital Logic Devices is provided. In one embodiment, a method of current management for a digital logic circuit is provided. The method comprises drawing power to drive a digital logic integrated circuit; performing one or more switching operations with the digital logic integrated circuit; learning at least one bypass current setpoint based on a voltage powering the digital logic integrated circuit while performing the one or more switching operations.

Abstract: Systems and methods for Current Management of Digital Logic Devices are provided. In one embodiment a method for calibrating a digital logic circuit current management system is provided. The method comprises activating one or more synchronous logic paths of a plurality of synchronous logic paths within the digital logic integrated circuit; sampling a voltage powering the digital logic integrated circuit while activating the one or more synchronous logic paths; storing one or more data samples representative of the sampled voltage; and calculating a bypass current setpoint based on the one or more data samples, wherein the bypass current setpoint specifies one or more bypass current characteristic to prevent the voltage powering the digital logic integrated circuit from dropping below a reference voltage.