Abstract: A system is provided for an improved cached STE invalidation. To track which STEs are updated, a memory is provided with a bitmap. Software identifies which STE are updated through the bitmap. Due to the update of the stored STE(s), corresponding STEs in a cache are stale. The software invalidates only the corresponding cached STEs as identified through the bitmap as opposed to invalidating all the cached STEs.

Abstract: A hypervisor may re-map a data stream from an address translation context bank to a termination context bank in response to detecting an address translation fault by a system memory management unit (SMMU). The termination context bank may be configured to terminate address translations, so that potential disruptions from further attempted address translations in the data stream may be avoided.

Abstract: A method for prioritizing commands in a command queue of a system memory management unit is provided. The method includes obtaining a first set of commands originating from a first virtual machine of a plurality of virtual machines and a second set of commands originating from a second virtual machine of the plurality of virtual machines, each of the plurality of virtual machines having a different priority ranking. The method further includes inserting the first set of commands and the second set of commands into the command queue of the system memory management unit based on the priority ranking of the first virtual machine and the priority ranking of the second virtual machine.