Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.

Abstract: A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on a hash instruction, the hash circuit receives from the register file and buffers within the state register a current state of a message being hashed. The state update circuit performs state update function on contents of the state register, where performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register. Following completion of all of the plurality of iterative rounds of processing, the execution unit stores contents of the state register to the register file as an updated state of the message.

Abstract: A processor includes an execution unit for executing a message padding instruction including an operand field indicating a register buffering a message block segment of a message block to be padded and a mode field indicating which hash functions is to be applied to the message block. The execution unit includes a padding circuit configured to receive a message block segment from a register indicated by the operand field, where the message block spans multiple registers in a register file. Based on which hash function is indicated by the mode field, the padding circuit selects a byte location in the message block segment at which to insert at least one padding byte and inserts the at least one padding byte at the byte location within the message block segment. The message block segment as padded by the at least one padding byte is written back to the register file.

Abstract: A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a Galois multiply instruction. The execution unit includes a carryless multiplier configured to multiply operands of the Galois multiply instruction to generate a product. The execution unit further includes a modular reduction circuit configured to receive the product and determine, based on a logical combination of the product and a fixed polynomial, a reduced product having a fewer number of bits than the product. The execution unit is configured to store the reduced product to the architected register file as a result of the Galois multiply instruction.

Abstract: A computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries; and an enforce below (ENFB) register field, each ENFB register field for each privilege level having one or more control aspect entries, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects. The PRVS register fields and the ENFB register fields are used to change the processor from a secure mode to a performance mode while running software applications.

Abstract: A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a key-generating instruction. The execution unit includes a key generation circuit that, responsive to a key-generating instruction, iteratively applies a cryptographic function to a sequence of iteration inputs beginning with an encryption key obtained from the architected register file and stores, within the architected register file, a decryption key obtained from at least one iteration of the cryptographic function.

Abstract: A method, computer program product, and/or system is disclosed for identifying special cases for testing an integrated circuit that includes defining interesting cases, preferably by a user; obtaining an instruction from an instruction set architecture (ISA); determining that there is an interesting case for the obtained instruction; computing (i) a size of the input space (I0) of the ISA, and (ii) an interesting case space (Ii) which is an input space leading to the interesting case for the obtained instruction; obtaining a special case fraction by dividing the interesting case space (Ii) by the input space (I0); determining a special case fraction (Ii)/(I0) is less than a threshold; and identifying, in response to the special case fraction being less than the threshold, the interesting case as a special case. In an approach the special case is documented.

Abstract: A computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries; and an enforce below (ENFB) register field, each ENFB register field for each privilege level having one or more control aspect entries, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects. The PRVS register fields and the ENFB register fields are used to change the processor from a secure mode to a performance mode while running software applications.

Abstract: A method, computer program product, and/or system is disclosed for identifying special cases for testing an integrated circuit that includes defining interesting cases, preferably by a user; obtaining an instruction from an instruction set architecture (ISA); determining that there is an interesting case for the obtained instruction; computing (i) a size of the input space (I0) of the ISA, and (ii) an interesting case space (Ii) which is an input space leading to the interesting case for the obtained instruction; obtaining a special case fraction by dividing the interesting case space (Ii) by the input space (I0); determining a special case fraction (Ii)/(I0) is less than a threshold; and identifying, in response to the special case fraction being less than the threshold, the interesting case as a special case. In an approach the special case is documented.

Abstract: A single input/output (I/O) controller for both secure partitionable endpoints (PEs) and non-secure PEs is enabled in a trusted execution environment (TEE) where secure memory portions are isolated from non-secure PEs. Security attributes for certain endpoints indicate secure memory access privilege of owning entities of the certain endpoints. A security monitor has exclusive access to the address translation control tables (TCE) stored in secure memory associated with a secure endpoint. When owning entity reassignment occurs, the endpoints are reinitialized to support a change in ownership from an outgoing owning entity having secure memory access and an incoming owning entity not having secure memory access.

Abstract: A hardware request of an application is detected. The Application executes on a virtualized computer system. It is determined that the hardware request includes a counter. The counter is to be performed by the virtualized computer system. The counter includes a counter value. The hardware request is intercepted before the it is processed by a hypervisor that hosts the virtualized computer system. The interception is based on the determining the hardware request includes the counter. The counter value is saved in a secure memory. The secure memory is obscured from the hypervisor. A scrambled counter value is generated. The hardware request is updated with the scrambled counter value. After the hardware request is updated it is provided to the hypervisor.

Abstract: Provided are systems, methods, and media for handling simulation of logic under test. An example method includes receiving a simulation model for the logic under test. Generating second logic that is configured to create a set of output logic signals based on an existing set of input logic signals of the logic under test. Rebuilding the simulation model based, at least in part, on the second logic. Examining a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic. Generating during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals.

Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.

Abstract: A computer system, processor, computer program product, and method for executing instructions in a software application that includes a processor that can be dynamically controlled, in response to a value set in a control register, to operate in either a secure mode or a performance mode. In the secure mode, the processor: upon encountering a secure mode entry instruction, computes an entry hash value using a hash function and stores the entry hash value; and upon encountering a secure mode exit instruction, computes an exit hash value, loads the entry hash value, and determines whether the entry hash value is the same as the exit hash value, and depending upon verification of the hash values can execute the return function or transfer control to the operating system. In the performance mode, the processor: executes both the secure mode entry instruction and the secure mode exit instruction as no-operations.

Abstract: A computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries; and an enforce below (ENFB) register field, each ENFB register field for each privilege level having one or more control aspect entries, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects. The PRVS register fields and the ENFB register fields are used to change the processor from a secure mode to a performance mode while running software applications.

Abstract: A processor and method for processing information is disclosed that in response to encountering a function entry instruction while running an application, computes an entry hash value using a hash of three hash input parameters, wherein one of the input parameters is a secret key stored in the special purpose register; and in response to encountering a function exit instruction, computes an exit hash value using the same three input parameters and the same hash used when computing the entry hash value; and determines if the entry hash value is the same as the exit hash value.

Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.

Abstract: An instruction may be associated with a memory address. During execution of the instruction, the memory address may be translated to a next level memory address. The instruction may also be marked for address tracing. If the instruction is marked for address tracing, then during execution of the instruction, the memory address and the next level memory address may be recorded.

Abstract: A system and method including a processor configured to, based on encountering an instruction that does not modify the architectural state of the processor, preferably a prefetch instruction, that is being executed by the processor, determine whether utilization of a first queue used in processing the instruction is over a first queue utilization limit; in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction; and in response to the first queue utilization being under the first queue utilization limit, at least partially process the prefetch instruction.

Abstract: A system and method including a processor configured to, based on encountering an instruction that does not modify the architectural state of the processor, preferably a prefetch instruction, that is being executed by the processor, determine whether utilization of a first queue used in processing the instruction is over a first queue utilization limit; in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction; and in response to the first queue utilization being under the first queue utilization limit, at least partially process the prefetch instruction.