Patents by Inventor Debapriya Sahu

Debapriya Sahu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12028096
    Abstract: A transmitter comprises an antenna array demultiplexor having a first input for an output signal, a second input for a control signal, a first output coupled to a first output pin, and a second output coupled to a second output pin. The antenna array demultiplexor provides the output signal to the first or second output based on the control signal. The first and second output pins are coupled to first and second antennae, respectively. In some implementations, the transmitter includes a transformer and a capacitor coupled in parallel between the first and second output pins, and the antenna array demultiplexor comprises a first switch coupled between the first output pin and a first ground pin, and a second switch coupled between the second output pin and a second ground pin. The first switch receives a second control signal, and the second switch receives an inverse of the second control signal.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: July 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rohit Chatterjee, Debapriya Sahu
  • Patent number: 11990916
    Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: May 21, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Meghna Agrawal, Debapriya Sahu
  • Publication number: 20240113724
    Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 4, 2024
    Inventors: Debapriya SAHU, Pranav SINHA, Meghna AGRAWAL
  • Patent number: 11936340
    Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: March 19, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Rohit Chatterjee
  • Patent number: 11888497
    Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: January 30, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Pranav Sinha, Meghna Agrawal
  • Publication number: 20230396259
    Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 7, 2023
    Inventors: Debapriya SAHU, Rittu SACHDEV
  • Patent number: 11777507
    Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: October 3, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Rittu Sachdev
  • Publication number: 20230308053
    Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 28, 2023
    Inventors: Debapriya Sahu, Rohit Chatterjee
  • Publication number: 20230275614
    Abstract: A wireless transceiver. The transceiver includes: (i) a transmit signal path; (ii) a calibration path, comprising a conductor to connect a calibration tone into the transmit signal path; (iii) a receive signal path, comprising a first data signal path to process a first data and a second data signal path, different than the first data signal path, to process a second data; (iv) a first capacitive coupling to couple a response to the calibration tone from the transmit signal path to the first data signal path; and (v) a second capacitive coupling to couple a response to the calibration tone from the transmit signal path to the second data signal path.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Inventors: Debapriya Sahu, Rohit Chatterjee, Srinivas Venkata Veeramreddi
  • Patent number: 11705867
    Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: July 18, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Rohit Chatterjee
  • Patent number: 11683066
    Abstract: A wireless transceiver. The transceiver includes: (i) a transmit signal path; (ii) a calibration path, comprising a conductor to connect a calibration tone into the transmit signal path; (iii) a receive signal path, comprising a first data signal path to process a first data and a second data signal path, different than the first data signal path, to process a second data; (iv) a first capacitive coupling to couple a response to the calibration tone from the transmit signal path to the first data signal path; and (v) a second capacitive coupling to couple a response to the calibration tone from the transmit signal path to the second data signal path.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: June 20, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Rohit Chatterjee, Srinivas Venkata Veeramreddi
  • Publication number: 20230094295
    Abstract: A transmitter comprises an antenna array demultiplexor having a first input for an output signal, a second input for a control signal, a first output coupled to a first output pin, and a second output coupled to a second output pin. The antenna array demultiplexor provides the output signal to the first or second output based on the control signal. The first and second output pins are coupled to first and second antennae, respectively. In some implementations, the transmitter includes a transformer and a capacitor coupled in parallel between the first and second output pins, and the antenna array demultiplexor comprises a first switch coupled between the first output pin and a first ground pin, and a second switch coupled between the second output pin and a second ground pin. The first switch receives a second control signal, and the second switch receives an inverse of the second control signal.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 30, 2023
    Inventors: Rohit CHATTERJEE, Debapriya SAHU
  • Publication number: 20230047618
    Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.
    Type: Application
    Filed: October 17, 2022
    Publication date: February 16, 2023
    Inventors: Meghna AGRAWAL, Debapriya SAHU
  • Publication number: 20220407537
    Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.
    Type: Application
    Filed: August 22, 2022
    Publication date: December 22, 2022
    Inventors: Debapriya SAHU, Pranav SINHA, Meghna AGRAWAL
  • Publication number: 20220360269
    Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 10, 2022
    Inventors: Debapriya SAHU, Rittu SACHDEV
  • Publication number: 20220345138
    Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has a first terminal and a second terminal. The compensation circuit has a third terminal and a fourth terminal. The third terminal is coupled to the first terminal, and the fourth terminal is coupled to the second terminal. The compensation circuit is configured to source current into the first terminal responsive to an increase in voltage on the second terminal, and to sink current from the first terminal responsive to a decrease in voltage on the second terminal.
    Type: Application
    Filed: June 1, 2021
    Publication date: October 27, 2022
    Inventors: Meghna AGRAWAL, Debapriya SAHU
  • Patent number: 11476859
    Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has a first terminal and a second terminal. The compensation circuit has a third terminal and a fourth terminal. The third terminal is coupled to the first terminal, and the fourth terminal is coupled to the second terminal. The compensation circuit is configured to source current into the first terminal responsive to an increase in voltage on the second terminal, and to sink current from the first terminal responsive to a decrease in voltage on the second terminal.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: October 18, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Meghna Agrawal, Debapriya Sahu
  • Patent number: 11424756
    Abstract: A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 23, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Debapriya Sahu, Pranav Sinha, Meghna Agrawal
  • Patent number: 11418201
    Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: August 16, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Rittu Sachdev
  • Publication number: 20220200534
    Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.
    Type: Application
    Filed: March 9, 2022
    Publication date: June 23, 2022
    Inventors: Debapriya Sahu, Rohit Chatterjee