Patents by Inventor Debaprosad Dutt

Debaprosad Dutt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Configuration of selected modules of a hardware block within a programmable logic device
    Patent number: 9710578
    Abstract: Various techniques are provided to configure embedded hardware resources of a programmable logic device (PLD). In one example, a method includes receiving configuration information for a plurality of hardware modules of an embedded hardware block of a PLD. The configuration information is received from a user of a computer system external to the PLD. The method also includes generating a plurality of models of the hardware block. The method also includes merging the generated models into a combined model of the hardware block. The combined model includes the configuration information received for the hardware modules of the hardware block. Related systems and additional techniques are also provided.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: July 18, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Debaprosad Dutt, Jamie Freed, Harish Venkatappa, Pradeep Lenka, Minghao Ni
  • CONFIGURATION OF SELECTED MODULES OF A HARDWARE BLOCK WITHIN A PROGRAMMABLE LOGIC DEVICE
    Publication number: 20140109031
    Abstract: Various techniques are provided to configure embedded hardware resources of a programmable logic device (PLD). In one example, a method includes receiving configuration information for a plurality of hardware modules of an embedded hardware block of a PLD. The configuration information is received from a user of a computer system external to the PLD. The method also includes generating a plurality of models of the hardware block. The method also includes merging the generated models into a combined model of the hardware block. The combined model includes the configuration information received for the hardware modules of the hardware block. Related systems and additional techniques are also provided.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 17, 2014
    Applicant: Lattice Semiconductor Corporation
    Inventors: Debaprosad Dutt, Jamie Freed, Harish Venkatappa, Pradeep Lenka, Minghao Ni
  • Method of integrated circuit manufacturing including cell assembly
    Patent number: 5229231
    Abstract: A method is described which reduces the size of the constraint graph used in assembling cells into a tiled module for integrated circuit manufacture. The smaller size significantly reduces the amount of time required to assemble the cells appropriately.
    Type: Grant
    Filed: August 30, 1991
    Date of Patent: July 20, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: Debaprosad Dutt, Chi-Yuan Lo