Abstract: A data warehouse engine (DWE) includes a central processing unit (CPU) core and a first data organization unit (DOU), where the first DOU is configured to aggregate read operations. The DWE also includes a first command queue coupled between the CPU core and the first DOU, where the first command queue is configured to convey commands from the CPU core to the first DOU.

Abstract: A computation system-on-a-chip (CSoC) includes a first scalable distributed real-time Data Warehousing (sdrDW) engine and a network interface coupled to the first sdrDW engine, where the network interface is coupled to an interconnect, and where the CSoC is configured to transmit a task request over the interconnect to a first networked bulk storage controller (NBSC) requesting that a task be performed on a bulk storage medium.

Abstract: A method includes receiving, by a real-time Data Warehouse (rDW) from a first task, a first dataset and spreading the first dataset to produce a first plurality of objects, where the first plurality of objects includes a first object and a second object. The method also includes storing the first object in a first location in an rDW data repository and storing the second object in a second location in the rDW data repository.

Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

Abstract: A system includes a plurality of compute modules and a first processor configured to implement a virtualization layer, where the virtualization layer is configured to support real time jobs. The system also includes a hardware support layer coupled between the plurality of compute modules and the virtualization layer, where the hardware support layer is configured to provide an interface between the virtualization layer and the plurality of compute modules.

Abstract: A data warehouse engine (DWE) includes a central processing unit (CPU) core and a first data organization unit (DOU), where the first DOU is configured to aggregate read operations. The DWE also includes a first command queue coupled between the CPU core and the first DOU, where the first command queue is configured to convey commands from the CPU core to the first DOU.

Abstract: A method includes obtaining, by a first processor, a first software architecture description file and obtaining, by the first processor, a platform independent model file. The method also includes obtaining, by the first processor, a platform architecture definition file and performing, by the first processor, a first source-to-source compilation in accordance with the first software architecture description file, the platform independent model file, and the platform architecture definition file, to produce generated interface code. Additionally, the method includes generating, by the first processor, run time code, in accordance with the generated interface code and running, by a second processor in real time, the run time code.

Abstract: A method includes receiving, by a real-time Data Warehouse (rDW) from a first task, a first dataset and spreading the first dataset to produce a first plurality of objects, where the first plurality of objects includes a first object and a second object. The method also includes storing the first object in a first location in an rDW data repository and storing the second object in a second location in the rDW data repository.

Abstract: A computation system-on-a-chip (CSoC) includes a first scalable distributed real-time Data Warehousing (sdrDW) engine and a network interface coupled to the first sdrDW engine, where the network interface is coupled to an interconnect, and where the CSoC is configured to transmit a task request over the interconnect to a first networked bulk storage controller (NBSC) requesting that a task be performed on a bulk storage medium.

Abstract: A method includes receiving, by a system on a chip (SoC) from a logically centralized controller, configuration information and reading, from a semantics aware storage module of the SoC, a data block in accordance with the configuration information. The method also includes performing scheduling to produce a schedule in accordance with the configuration information and writing the data block to an input data queue in accordance with the schedule to produce a stored data block. Additionally, the method includes writing a tag to an input tag queue to produce a stored tag, where the tag corresponds to the data block.

Abstract: A system includes a plurality of compute modules and a first processor configured to implement a virtualization layer, where the virtualization layer is configured to support real time jobs. The system also includes a hardware support layer coupled between the plurality of compute modules and the virtualization layer, where the hardware support layer is configured to provide an interface between the virtualization layer and the plurality of compute modules.

Abstract: A method for predetermining whether a cancer has a probability to become metastatic or recurrent, having the steps of: obtaining a sample cell population; assaying the sample cell population; detecting the rate of change of the sample cell population's pH over time; and comparing the pH change versus a predetermined pH rate of change. Also provided is a method of treating a patient having the steps of: isolating a cancer stem cell from a patient; culturing the cancer stem cell to produce a pool of descendant cells; culturing cells from the pool of descendant cells in the presence at least one compound among: anti-cancer drugs, myeloablative, chemotherapeutic, and immunotherapeutic agents, and a combination thereof; assaying over time, during the step of culturing, hydrogen ion concentration in the set of cells; and selecting a candidate therapeutic regimen for the patient based on a result of the assaying step.

Abstract: A system and method for designing ICs, including the steps of: analyzing and optimizing a target IC design based on design-specific objectives; partitioning the optimized target IC design into pre-defined standard-cells from one or more libraries and creating design-specific cells specifically having unique functionality and characteristics not found amongst the standard-cells; identifying and determining a minimal subset of the standard-cells and design-specific cells, the interconnection of which represents the target IC design; generating the necessary views, including layout and characterizing of the design-specific cells included in a unique, minimal subset, wherein the IC design is subject to objectives and constraints of the target IC.

Abstract: The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the design-specific cell, mapping a transistor-level representation of the design-specific cell, wherein the mapping is based on at least one, but perhaps plural design specifications, and evaluating the transistor-level representation of the design-specific cell for satisfaction of the design specification.

Abstract: A method and system for constructing, designing, and using a family of logic circuits based on methods of interconnecting transistors (or more generally, switches). The method includes the selective use of functionally redundant transistors to achieve target objectives, such as speed of operation, power dissipation, control over switching capacitances, noise characteristics and signal integrity. In accordance with the present invention, multiple topologies may be incorporated into the implementation of a single dynamic transistor topology. The logic circuit family provides flexibility by implementing different topologies for the various functionally redundant sub-networks of transistors. The method is applicable to any network of transistors whose characteristics depend, at least in part, on its implementation topology.

Abstract: The present invention relates to a method for minimizing the number of standard cells required to implement a digital circuit and for improving the characterization of new standard cells based on their context/environment. In addition, a systematic method that utilizes detailed characterization at the transistor-level on critical areas of the design for improved characterization and optimization of the entire design is presented.

Abstract: The present invention relates to a method for minimizing the number of standard cells required to implement a digital circuit and for improving the characterization of new standard cells based on their context/environment. In addition, a systematic method that utilizes detailed characterization at the transistor-level on critical areas of the design for improved characterization and optimization of the entire design is presented.

Abstract: A method and system for constructing, designing, and using a family of logic circuits based on methods of interconnecting transistors (or more generally, switches). The method includes the selective use of functionally redundant transistors to achieve target objectives, such as speed of operation, power dissipation, control over switching capacitances, noise characteristics, signal integrity etc. In accordance with the present invention, multiple topologies may be incorporated into the implementation of a single dynamic transistor topology. The logic circuit family provides flexibility by implementing different topologies for the various functionally redundant sub-networks of transistors. The method is applicable to any network of transistors whose characteristics depend, at least in part, on its implementation topology.

Abstract: This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller controls the switch state of the programmable switch. The programmable switch is controlled to selectively connect the first test access port to the embedded core circuits. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test. The test access port controller can regain control of the first test access port and disconnect all of the embedded core circuits when in snoopy states.