Patents by Inventor Debashish BASU

Debashish BASU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12271429
    Abstract: Enhanced methods for improving the performance of classifiers are described. A ground-truth labeled dataset is accessed. A classifier predicts a predicted label for datapoints of the dataset. A confusion matrix for the dataset and classifier is generated. A credibility interval is determined for a performance metric for each label. A first labels with a sufficiently large credibility interval is identified. A second label is identified, where the classifier is likely to confuse, in its predictions, the first label with the second label. The identification of the second label is based on instances of incorrect label predictions of the classifier for the first and/or the second labels. The classifier is updated based on a new third label that includes an aggregation of the first label and the second label. The updated classifier model predicts the third label for any datapoint that the classifier previously predicted the first or second labels.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: April 8, 2025
    Assignee: Adobe Inc.
    Inventors: Debraj Debashish Basu, Ganesh Satish Mallya, Shankar Venkitachalam, Deepak Pai
  • Publication number: 20250078220
    Abstract: In implementation of techniques for generating salient regions based on multi-resolution partitioning, a computing device implements a salient object system to receive a digital image including a salient object. The salient object system generates a first mask for the salient object by partitioning the digital image into salient and non-salient regions. The salient object system also generates a second mask for the salient object that has a resolution that is different than the first mask by partitioning a resampled version of the digital image into salient and non-salient regions. Based on the first mask and the second mask, the salient object system generates an indication of a salient region of the digital image using a machine learning model. The salient object system then displays the indication of the salient region in a user interface.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 6, 2025
    Applicant: Adobe Inc.
    Inventors: Sriram Ravindran, Debraj Debashish Basu
  • Patent number: 12190621
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media that utilize intelligent contextual bias weights for informing keyphrase relevance models to extract keyphrases. For example, the disclosed systems generate a graph from a digital document by mapping words from the digital document to nodes of the graph. In addition, the disclosed systems determine named entity bias weights for the nodes of the graph utilizing frequencies with which the words corresponding to the nodes appear within named entities identified from the digital document. Moreover, the disclosed systems generate a keyphrase summary for the digital document utilizing the graph and a machine learning model biased according to the named entity bias weights for the nodes of the graph.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: January 7, 2025
    Assignee: Adobe Inc.
    Inventors: Debraj Debashish Basu, Shankar Venkitachalam, Vinh Khuc, Deepak Pai
  • Publication number: 20240386627
    Abstract: In accordance with the described techniques, an image transformation system receives an input image and a text prompt, and leverages a generator network to edit the input image based on the text prompt. The generator network includes a plurality of layers configured to perform respective edits. A plurality of masks are generated based on the text prompt that define local edit regions, respectively, of the input image for respective layers of the generator network. Further, the generator network generates an edited image by editing the input image based on the plurality of masks, the respective edits of the respective layers, and the text prompt.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Applicant: Adobe Inc.
    Inventors: Ambareesh Revanur, Debraj Debashish Basu, Shradha Agrawal, Dhwanit Agarwal, Deepak Pai
  • Publication number: 20240312087
    Abstract: Systems and methods for document processing are provided. One aspect of the systems and methods includes identifying a theme and an input image of a product. Another aspect of the systems and methods includes generating an output image depicting the product and the theme based on the input image using an image generation model that is trained to generate images consistent with a brand. Another aspect of the systems and methods includes generating text based on the product and the theme using a text generation model. Another aspect of the systems and methods includes generating custom content consistent with the brand and the theme based on the output image and the text.
    Type: Application
    Filed: July 28, 2023
    Publication date: September 19, 2024
    Inventors: Shradha Agrawal, Debraj Debashish Basu, Deepak Pai, Nimish Srivastav, Meghanath Macha, Ambareesh Revanur
  • Publication number: 20230282018
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media that utilize intelligent contextual bias weights for informing keyphrase relevance models to extract keyphrases. For example, the disclosed systems generate a graph from a digital document by mapping words from the digital document to nodes of the graph. In addition, the disclosed systems determine named entity bias weights for the nodes of the graph utilizing frequencies with which the words corresponding to the nodes appear within named entities identified from the digital document. Moreover, the disclosed systems generate a keyphrase summary for the digital document utilizing the graph and a machine learning model biased according to the named entity bias weights for the nodes of the graph.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 7, 2023
    Inventors: Debraj Debashish Basu, Shankar Venkitachalam, Vinh Khuc, Deepak Pai
  • Patent number: 11652045
    Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Mohit K. Haran, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An, Debashish Basu, Kilhyun Bang, Jason W. Klaus, Reken Patel, Charles Henry Wallace, James Jeong, Ruth Amy Brain
  • Publication number: 20230143021
    Abstract: Integrated circuit interconnect structure compatible with single damascene techniques and that includes a non-copper via comprising metal(s) of low resistivity that can be deposited at low temperature in a manner that also ensures good adhesion. Metal(s) suitable for the non-copper via may have BCC crystallinity that can advantageously template favorable crystallinity within a diffusion barrier of the upper-level interconnect feature, further reducing electrical resistance of an interconnect structure.
    Type: Application
    Filed: November 8, 2021
    Publication date: May 11, 2023
    Applicant: Intel Corporation
    Inventors: Daniel B. OBrien, Jeffrey S. Leib, James Y. Jeong, Chia-Hong Jan, Peng Bai, Seungdo An, Pavel S. Plekhanov, Debashish Basu
  • Publication number: 20230101107
    Abstract: An integrated circuit structure comprises a first metal layer having first conductive features. A second metal layer has second conductive features. A via layer is in an insulating layer between the first metal layer and the second metal layer. First vias and second vias are formed in the insulating layer. The first vias have a first aspect ratio greater than a second aspect ratio of the second vias. A barrier-less metal partially fills the first vias and fills the second vias. A pure metal fills a remainder of the first vias.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: AKM Shaestagir CHOWDHURY, Debashish BASU, Githin F. ALAPATT, Justin E. MUELLER, James Y. JEONG
  • Patent number: 11610085
    Abstract: In some examples, a prototype model that includes a representative subset of data points (e.g., inputs and output classifications) of a machine learning model is analyzed to efficiently interpret the machine learning model's behavior. Performance metrics such as a critic fraction, local explanation scores, and global explanation scores are determined. A local explanation score capture an importance of a feature of a test point to the machine learning model determining a particular class for the test point and is computed by comparing a value of a feature of a test point to values for prototypes of the prototype model. Using a similar approach, global explanation scores may be computed for features by combining local explanation scores for data points. A critic fraction may be computed to quantify a misclassification rate of the prototype model, indicating the interpretability of the model.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: March 21, 2023
    Assignee: ADOBE INC.
    Inventors: Deepak Pai, Debraj Debashish Basu, Joshua Alan Sweetkind-Singer
  • Publication number: 20220300557
    Abstract: Enhanced methods for improving the performance of classifiers are described. A ground-truth labeled dataset is accessed. A classifier predicts a predicted label for datapoints of the dataset. A confusion matrix for the dataset and classifier is generated. A credibility interval is determined for a performance metric for each label. A first labels with a sufficiently large credibility interval is identified. A second label is identified, where the classifier is likely to confuse, in its predictions, the first label with the second label. The identification of the second label is based on instances of incorrect label predictions of the classifier for the first and/or the second labels. The classifier is updated based on a new third label that includes an aggregation of the first label and the second label. The updated classifier model predicts the third label for any datapoint that the classifier previously predicted the first or second labels.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventors: Debraj Debashish Basu, Ganesh Satish Mallya, Shankar Venkitachalam, Deepak Pai
  • Publication number: 20220051975
    Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Applicant: Intel Corporation
    Inventors: Mohit K. Haran, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An, Debashish Basu, Kilhyun Bang, Jason W. Klaus, Reken Patel, Charles Henry Wallace, James Jeong, Ruth Amy Brain
  • Patent number: 11211324
    Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Mohit K. Haran, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An, Debashish Basu, Kilhyun Bang, Jason W. Klaus, Reken Patel, Charles Henry Wallace, James Jeong, Ruth Amy Brain
  • Patent number: 11145541
    Abstract: Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Reken Patel, Hyunsoo Park, Mohit K. Haran, Debashish Basu, Curtis W. Ward, Ruth A. Brain
  • Publication number: 20210082805
    Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Intel Corporation
    Inventors: Mohit K. Haran, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An, Debashish Basu, Kilhyun Bang, Jason W. Klaus, Reken Patel, Charles Henry Wallace, James Jeong, Ruth Amy Brain
  • Publication number: 20200279140
    Abstract: In some examples, a prototype model that includes a representative subset of data points (e.g., inputs and output classifications) of a machine learning model is analyzed to efficiently interpret the machine learning model's behavior. Performance metrics such as a critic fraction, local explanation scores, and global explanation scores are determined. A local explanation score capture an importance of a feature of a test point to the machine learning model determining a particular class for the test point and is computed by comparing a value of a feature of a test point to values for prototypes of the prototype model. Using a similar approach, global explanation scores may be computed for features by combining local explanation scores for data points. A critic fraction may be computed to quantify a misclassification rate of the prototype model, indicating the interpretability of the model.
    Type: Application
    Filed: February 28, 2019
    Publication date: September 3, 2020
    Inventors: Deepak Pai, Debraj Debashish Basu, Joshua Alan Sweetkind-Singer
  • Publication number: 20200185271
    Abstract: Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening.
    Type: Application
    Filed: September 30, 2017
    Publication date: June 11, 2020
    Inventors: Charles H. WALLACE, Reken PATEL, Hyunsoo PARK, Mohit K. HARAN, Debashish BASU, Curtis W. WARD, Ruth A. Brain