Patents by Inventor Debashree Ghosh

Debashree Ghosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10769540
    Abstract: An example method for building a model to predict rare events is disclosed. The example disclosed herein comprises receiving a plurality of historical input logs wherein each log includes at least one key variable and unstructured data. The example further comprises applying text mining techniques to the unstructured data to obtain at least one predictor based on the unstructured data. The example further comprises creating a rare events prediction model based on the at least one key variable and the at least one predictor.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: September 8, 2020
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Ajeet Subramanian, Debashree Ghosh, Swati Gupta
  • Publication number: 20180314954
    Abstract: An example method for building a model to predict rare events is disclosed. The example disclosed herein comprises receiving a plurality of historical input logs wherein each log includes at least one key variable and unstructured data. The example further comprises applying text mining techniques to the unstructured data to obtain at least one predictor based on the unstructured data. The example further comprises creating a rare events prediction model based on the at least one key variable and the at least one predictor.
    Type: Application
    Filed: April 27, 2017
    Publication date: November 1, 2018
    Inventors: Ajeet Subramanian, Debashree Ghosh, Swati Gupta
  • Patent number: 6191618
    Abstract: A domino logic circuit includes a first domino gate that evaluates one or more inputs responsive to a clock signal, a reset gate, and a second domino gate having a first input coupled to the output of the first domino gate. A first input of a reset gate is coupled to the output of the first domino gate, with a second input of the reset gate being coupled to the output of the second domino gate. The reset gate outputs a precharge signal coupled to a second input of the second domino gate when the second domino gate is discharged and the output of the first domino gate changes state such that a high-to-low transition occurs at the first input of the second domino gate.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventors: Eric Gayles, Bharat Bhushan, Debashree Ghosh