Patents by Inventor Debasish Chandra
Debasish Chandra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10108548Abstract: In one aspect, a processor has a register file, a private Level 1 (L1) cache, and an interface to a shared memory hierarchy (e.g., an Level 2 (L2) cache and so on). The processor has a Load Store Unit (LSU) that handles decoded load and store instructions. The processor may support out of order and multi-threaded execution. As store instructions arrive at the LSU for processing, the LSU determines whether a counter, from a set of counters, is allocated to a cache line affected by each store. If not, the LSU allocates a counter. If so, then the LSU updates the counter. Also, in response to a store instruction, affecting a cache line neighboring a cache line that has a counter that meets a criteria, the LSU characterizes that store instruction as one to be effected without obtaining ownership of the effected cache line, and provides that store to be serviced by an element of the shared memory hierarchy.Type: GrantFiled: August 18, 2015Date of Patent: October 23, 2018Assignee: MIPS Tech, LLCInventors: Ranjit J. Rozario, Era Nangia, Debasish Chandra, Ranganathan Sudhakar
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Patent number: 9940168Abstract: Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.Type: GrantFiled: January 12, 2017Date of Patent: April 10, 2018Assignee: MIPS Tech, LLCInventor: Debasish Chandra
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Publication number: 20170123853Abstract: Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.Type: ApplicationFiled: January 12, 2017Publication date: May 4, 2017Inventor: Debasish CHANDRA
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Patent number: 9563476Abstract: Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.Type: GrantFiled: August 27, 2015Date of Patent: February 7, 2017Assignee: Imagination Technologies, LLCInventor: Debasish Chandra
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Publication number: 20160055083Abstract: In one aspect, a processor has a register file, a private Level 1 (L1) cache, and an interface to a shared memory hierarchy (e.g., an Level 2 (L2) cache and so on). The processor has a Load Store Unit (LSU) that handles decoded load and store instructions. The processor may support out of order and multi-threaded execution. As store instructions arrive at the LSU for processing, the LSU determines whether a counter, from a set of counters, is allocated to a cache line affected by each store. If not, the LSU allocates a counter. If so, then the LSU updates the counter. Also, in response to a store instruction, affecting a cache line neighboring a cache line that has a counter that meets a criteria, the LSU characterizes that store instruction as one to be effected without obtaining ownership of the effected cache line, and provides that store to be serviced by an element of the shared memory hierarchy.Type: ApplicationFiled: August 18, 2015Publication date: February 25, 2016Inventors: Ranjit J. Rozario, Era Nangia, Debasish Chandra, Ranganathan Sudhakar
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Publication number: 20150370605Abstract: Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.Type: ApplicationFiled: August 27, 2015Publication date: December 24, 2015Inventor: Debasish CHANDRA
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Patent number: 9135067Abstract: Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.Type: GrantFiled: February 28, 2013Date of Patent: September 15, 2015Assignee: MIPS Technologies, Inc.Inventor: Debasish Chandra
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Publication number: 20140258697Abstract: A processor includes a multiple stage pipeline with a scheduler with a wakeup block and select logic. The wakeup block is configured to wake, in a first cycle, all instructions dependent upon a first selected instruction to form a wake instruction set. In a second cycle, the wakeup block wakes instructions dependent upon the wake instruction set to augment the wake instruction set. The select logic selects instructions from the wake instruction set based upon program order.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: MIPS TECHNOLOGIES, INC.Inventors: Ranganathan Sudhakar, Debasish Chandra, Qian Wang
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Publication number: 20140245317Abstract: Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Applicant: MIPS Technologies, Inc.Inventor: Debasish CHANDRA
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Patent number: 8627044Abstract: The described embodiments include a processor that determines instructions that can be issued based on unresolved data dependencies. In an issue unit in the processor, the processor keeps a record of each instruction that is directly or indirectly dependent on a base instruction. Upon determining that the base instruction has been deferred, the processor monitors instructions that are being issued from an issue queue to an execution unit for execution. Upon determining that an instruction from the record has reached a head of the issue queue, the processor immediately issues the instruction from the issue queue.Type: GrantFiled: October 6, 2010Date of Patent: January 7, 2014Assignee: Oracle International CorporationInventors: Shailender Chaudhry, Richard Thuy Van, Robert E. Cypher, Debasish Chandra
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Publication number: 20120089819Abstract: The described embodiments include a processor that determines instructions that can be issued based on unresolved data dependencies. In an issue unit in the processor, the processor keeps a record of each instruction that is directly or indirectly dependent on a base instruction. Upon determining that the base instruction has been deferred, the processor monitors instructions that are being issued from an issue queue to an execution unit for execution. Upon determining that an instruction from the record has reached a head of the issue queue, the processor immediately issues the instruction from the issue queue.Type: ApplicationFiled: October 6, 2010Publication date: April 12, 2012Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Shailender Chaudhry, Richard Thuy Van, Robert E. Cypher, Debasish Chandra