Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.

Abstract: Method and system for providing increased frequency of flash memories compatible to Serial Peripheral Interface (SPI) bus protocol by delayed data capturing so that system boot loader down load time reduces for a given memory configuration. Methods and systems are provided for operating the memory at the device rated frequency.

Abstract: A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.

Abstract: A bus interconnect for interconnecting one or more master devices with one or more slave devices in a system includes at least one slave interface module adapted for communicating with a corresponding one of the master devices and at least one master interface module adapted for communicating with a corresponding one of the slave devices. The bus interconnect further includes a configurable response module coupled with the slave interface module. The configurable response module is operative to generate different configurable responses associated with access requests to corresponding portions of an address space of the system.

Abstract: A memory management apparatus includes a first controller adapted to receive an input data sequence including one or more data frames and operative: to separate each of the data frames into a payload data portion and a header portion; to store the payload data portion in at least one available memory location in a physical storage space; and to store in a logical storage space the header portion along with at least one associated index indicating where in the physical storage space the corresponding payload data portion resides. The apparatus further includes a second controller operative, as a function of a data read request, to access the physical storage space using the header portion and associated index from the logical storage space to retrieve the corresponding payload data portion and to combine the header portion with the payload data portion to generate a response to the data read request.

Abstract: An electronic storage system includes a first cylindrical storage area. The first cylindrical storage area is configured to rotate about an axis. The first cylindrical storage area includes a first storage surface. The storage system further includes a first access head, configured to access information stored on the first storage surface, and a first head arm. The first access head is disposed on the first head arm. A corresponding method, cylindrical storage area, and head access assembly are also provided.

Abstract: A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.

Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.