Patents by Inventor Debo Olaosebikan
Debo Olaosebikan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11545204Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.Type: GrantFiled: July 2, 2021Date of Patent: January 3, 2023Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11532635Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.Type: GrantFiled: June 11, 2021Date of Patent: December 20, 2022Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11532342Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.Type: GrantFiled: July 2, 2021Date of Patent: December 20, 2022Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11527277Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.Type: GrantFiled: June 4, 2021Date of Patent: December 13, 2022Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11527278Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.Type: GrantFiled: July 2, 2021Date of Patent: December 13, 2022Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11521667Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.Type: GrantFiled: June 25, 2021Date of Patent: December 6, 2022Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11521666Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.Type: GrantFiled: June 11, 2021Date of Patent: December 6, 2022Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11514967Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.Type: GrantFiled: July 2, 2021Date of Patent: November 29, 2022Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11514966Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.Type: GrantFiled: July 2, 2021Date of Patent: November 29, 2022Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11501813Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.Type: GrantFiled: July 30, 2021Date of Patent: November 15, 2022Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11423967Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.Type: GrantFiled: June 25, 2021Date of Patent: August 23, 2022Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11152343Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.Type: GrantFiled: May 31, 2019Date of Patent: October 19, 2021Assignee: Kepler Computing, Inc.Inventors: Rajeev Kumar Dokania, Sasikanth Manipatruni, Amrita Mathuriya, Debo Olaosebikan
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Patent number: 11043472Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.Type: GrantFiled: May 31, 2019Date of Patent: June 22, 2021Assignee: Kepler Compute Inc.Inventors: Rajeev Kumar Dokania, Sasikanth Manipatruni, Amrita Mathuriya, Debo Olaosebikan