Abstract: Implementations of the present disclosure disclose a memory and an operating method thereof, a memory system, and an electronic device. The memory includes a memory cell array and a peripheral circuit coupled with the memory cell array. The peripheral circuit includes: a temperature sensing circuit configured to sense a temperature of the memory and generate a temperature signal based on the sensed temperature; a control logic circuit configured to determine a target refresh period based on the temperature signal and a mapping table, wherein the mapping table includes a plurality of preset temperature signals and a plurality of preset refresh periods in a one-to-one correspondence; and a refresh control circuit configured to adjust a refresh period of a refresh signal to the target refresh period, wherein the refresh signal is configured to indicate performing a refresh operation on the memory cell array.

Abstract: Examples of the present disclosure provide a memory, an operation method thereof, a memory system and an electronic apparatus. The memory includes a peripheral circuit and the peripheral circuit includes a first register circuit configured to store a plurality of initial refresh rates that are in one-to-one correspondence to a plurality of initial temperature sections; a temperature sensing circuit configured to sense a temperature of the memory and generate a temperature signal based on the sensed temperature; and a control logic circuit configured to determine a target configuration refresh rate based on the temperature signal and a configuration mapping table and adjust a target initial refresh rate of the plurality of initial refresh rates to the target configuration refresh rate, wherein the configuration mapping table includes a plurality of configuration temperature sections and a plurality of configuration refresh rates that are in one-to-one correspondence.

Abstract: According to one aspect of the present disclosure, a memory is provided. The memory may include a row hammer control circuit including a plurality of counters. Each of the plurality of counters may count a number of accesses of one memory row. Each of the plurality of counters may be configured to generate a first count value. The memory may include an adjustment circuit connected with the plurality of counters. The adjustment circuit may reset each of the plurality of counters when each of a plurality of first count values reaches a target threshold. The adjustment circuit may adjust each of the first count values by a same offset value to generate a plurality of second count values. The row hammer control circuit may determine a target memory row according to the plurality of second count values.

Abstract: Examples of the present disclosure provide memory devices and an operation method thereof. The memory device includes: a memory cell array; a control logic circuit coupled with the memory cell array and configured to receive a command address signal, output a first control signal at a first time instant, and output a second control signal at a second time instant, wherein the first time instant is different from the second time instant; and a clock generation circuit configured to receive a first clock signal, the first control signal and the second control signal, be pre-charged according to the first control signal, and perform frequency division processing on the first clock signal according to the second control signal to output a second clock signal, wherein the first clock signal is different from the second clock signal.

Abstract: A method of configuring an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice that have one or more pads coupled in common, includes determining, by each of the non-volatile memory dice whether that non-volatile memory die is a target or a non-target for a memory operation; setting, by each of the non-volatile memory die that determines it is a target, a first on-die termination configuration value; setting, by each of the non-volatile memory die that determines it is a non-target, a second on-die termination configuration value; configuring, by each of the target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value; and concurrently with the configuring by each target non-volatile memory die, configuring, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least

Abstract: Examples of the present application provide a memory device and operating method thereof, a memory system, and a sensing circuit. Wherein the memory device includes: an array of memory cells; a first sensing circuit coupled to the array of memory cells through a first pair of data lines; a second sensing circuit coupled to the first pair of data lines through a second pair of data lines; an isolation circuit located between the first pair of data lines and the second pair of data lines; a control circuit configured to: in the first sensing phase, control the first sensing circuit to amplify the data signal to the first sensing signal, and control the isolation circuit to connect the first pair of data lines and the second pair of data lines.

Abstract: Examples of the present disclosure include a memory device, a control method thereof, and a memory system. The memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes memory rows each including memory cells coupled to one word line. The peripheral circuit is configured to determine, in response to a read command, whether address information same as first address information of a first memory row corresponding to the read command exists in a refresh table. The refresh table stores pieces of address information each corresponding to one of the memory rows. The peripheral circuit is configured to delete the address information same as the first address information from the refresh table in response to the address information same as the first address information existing in the refresh table.

Abstract: Examples of the present disclosure provide a memory, an operation method thereof, a memory system and an electronic apparatus. The memory includes a peripheral circuit and the peripheral circuit includes a first register circuit configured to store a plurality of initial refresh rates that are in one-to-one correspondence to a plurality of initial temperature sections; a temperature sensing circuit configured to sense a temperature of the memory and generate a temperature signal based on the sensed temperature; and a control logic circuit configured to determine a target configuration refresh rate based on the temperature signal and a configuration mapping table and adjust a target initial refresh rate of the plurality of initial refresh rates to the target configuration refresh rate, wherein the configuration mapping table includes a plurality of configuration temperature sections and a plurality of configuration refresh rates that are in one-to-one correspondence.

Abstract: A method of configuring an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice that have one or more pads coupled in common, includes determining, by each of the non-volatile memory dice whether that non-volatile memory die is a target or a non-target for a memory operation; setting, by each of the non-volatile memory die that determines it is a target, a first on-die termination configuration value; setting, by each of the non-volatile memory die that determines it is a non-target, a second on-die termination configuration value; configuring, by each of the target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value; and concurrently with the configuring by each target non-volatile memory die, configuring, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least

Abstract: Implementations of the present disclosure disclose a memory and an operating method thereof, a memory system, and an electronic device. The memory includes a memory cell array and a peripheral circuit coupled with the memory cell array. The peripheral circuit includes: a temperature sensing circuit configured to sense a temperature of the memory and generate a temperature signal based on the sensed temperature; a control logic circuit configured to determine a target refresh period based on the temperature signal and a mapping table, wherein the mapping table includes a plurality of preset temperature signals and a plurality of preset refresh periods in a one-to-one correspondence; and a refresh control circuit configured to adjust a refresh period of a refresh signal to the target refresh period, wherein the refresh signal is configured to indicate performing a refresh operation on the memory cell array.

Abstract: According to one aspect of the present disclosure, a memory is provided. The memory may include a row hammer control circuit including a plurality of counters. Each of the plurality of counters may count a number of accesses of one memory row. Each of the plurality of counters may be configured to generate a first count value. The memory may include an adjustment circuit connected with the plurality of counters. The adjustment circuit may reset each of the plurality of counters when each of a plurality of first count values reaches a target threshold. The adjustment circuit may adjust each of the first count values by a same offset value to generate a plurality of second count values. The row hammer control circuit may determine a target memory row according to the plurality of second count values.

Abstract: A method of configuring an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice that have one or more pads coupled in common, includes determining, by each of the non-volatile memory dice whether that non-volatile memory die is a target or a non-target for a memory operation; setting, by each of the non-volatile memory die that determines it is a target, a first on-die termination configuration value; setting, by each of the non-volatile memory die that determines it is a non-target, a second on-die termination configuration value; configuring, by each of the target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value; and concurrently with the configuring by each target non-volatile memory die, configuring, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least