Patents by Inventor Deboleena Minz
Deboleena Minz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11709522Abstract: Embodiments herein describe techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as “cards”) by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds.Type: GrantFiled: September 16, 2020Date of Patent: July 25, 2023Assignee: XILINX, INC.Inventors: Sebastian Turullols, Ravinder Sharma, Siva Santosh Kumar Pyla, Raj Kumar Rampelli, Deboleena Minz Sakalley, Nilay Shah
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Publication number: 20230133020Abstract: Various approaches for deploying and controlling distributed accelerated compute operations with the use of infrastructure processing units (IPUs) and similar networked processing units are disclosed. A system for orchestrating acceleration functions in a network compute mesh is configured to access a flowgraph, the flowgraph including data producer-consumer relationships between a plurality of tasks in a workload; identify available artifacts and resources to execute the artifacts to complete each of the plurality of tasks, wherein an artifact is an instance of a function to perform a task of the plurality of tasks; determine a configuration assigning artifacts and resources to each of the plurality of tasks in the flowgraph; and schedule, based on the configuration, the plurality of tasks to execute using the assigned artifacts and resources.Type: ApplicationFiled: December 29, 2022Publication date: May 4, 2023Inventors: Deboleena Minz Sakalley, Kshitij Arun Doshi, Francesc Guim Bernat
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Patent number: 10210089Abstract: A method and apparatus are provided for controlling data flow by storing variable length encoded information bits in a circular buffer in a write operation to a virtual write address comprising a first wrap bit value appended by a current write address within the buffer address range and generating an interrupt alarm if the virtual write address crosses a virtual alarm address comprising a second wrap bit value appended by an alarm address within the buffer address range, where the first and second wrap bit values each toggle between first and second values every time the current write address or alarm address, respectively, wraps around the circular buffer, thereby synchronizing data flow in the circular buffer and/or preventing buffer overflow.Type: GrantFiled: June 18, 2015Date of Patent: February 19, 2019Assignee: NXP USA, Inc.Inventors: Stephan M. Herrmann, Ritesh Agrawal, Aman Arora, Jeetendra Kumar Gupta, Snehlata Gutgutia, Deboleena Minz Sakalley
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Patent number: 9665423Abstract: A technique for providing end-to-end error detection coding between a requesting module and a memory module have been disclosed. A method includes translating a first logical address of a memory request to a physical address. The method includes translating an error control code and data associated with the memory request between a first format and a second format. The error control code and data having the first format is generated based on the first logical address. The error control code and data having the second format is generated based on a second address. The method includes generating an error indicator based on the error control code, the data, and one of the first logical address and the second address.Type: GrantFiled: June 15, 2015Date of Patent: May 30, 2017Assignee: NXP USA, Inc.Inventors: Derek Beattie, Mark Jordan, Ray Marshall, Deboleena Minz Sakalley
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Publication number: 20170070768Abstract: A video stream decoder for decoding a multiple parallel-input video streams from multiple video cameras permits continuance of the decoding process even if one of the streams has stalled or if a start code of a currently active stream has become corrupted. A counter triggers a stream switching module to switch to a different input video stream on a round-robin or priority basis after a preset time period elapsed if no start code of a currently active stream has been detected.Type: ApplicationFiled: September 6, 2015Publication date: March 9, 2017Inventors: DEBOLEENA MINZ SAKALLEY, SNEHLATA GUTGUTIA, AMAN ARORA, DIRK WENDEL, RITESH AGRAWAL, JEETENDRA GUPTA
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Publication number: 20160371182Abstract: A method and apparatus are provided for controlling data flow by storing variable length encoded information bits in a circular buffer in a write operation to a virtual write address comprising a first wrap bit value appended by a current write address within the buffer address range and generating an interrupt alarm if the virtual write address crosses a virtual alarm address comprising a second wrap bit value appended by an alarm address within the buffer address range, where the first and second wrap bit values each toggle between first and second values every time the current write address or alarm address, respectively, wraps around the circular buffer, thereby synchronizing data flow in the circular buffer and/or preventing buffer overflow.Type: ApplicationFiled: June 18, 2015Publication date: December 22, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Stephan M. Herrmann, Ritesh Agrawal, Aman Arora, Jeetendra Kumar Gupta, Snehlata Gutgutia, Deboleena Minz Sakalley
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Publication number: 20160364289Abstract: A technique for providing end-to-end error detection coding between a requesting module and a memory module have been disclosed. A method includes translating a first logical address of a memory request to a physical address. The method includes translating an error control code and data associated with the memory request between a first format and a second format. The error control code and data having the first format is generated based on the first logical address. The error control code and data having the second format is generated based on a second address. The method includes generating an error indicator based on the error control code, the data, and one of the first logical address and the second address.Type: ApplicationFiled: June 15, 2015Publication date: December 15, 2016Inventors: Derek BEATTIE, Mark JORDAN, Ray MARSHALL, Deboleena Minz SAKALLEY
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Patent number: 9251906Abstract: A method and circuit for generating a shifted strobe signal for sampling data read from a memory device includes generating an instantiation of a shifted strobe signal by applying both a coarse adjustment delay value and a fine adjustment delay value to a clock. Data read from a predetermined, programmed memory location or locations of the memory device is sampled using the shifted strobe signal. At least one of the applying steps is repeated and the read data is sampled again using the current instantiation of the shifted strobe signal. The process is repeated until the current instantiation of the shifted strobe signal is aligned with a valid data window of the memory device. The method can be used in both single data rate and double data rate applications.Type: GrantFiled: May 18, 2015Date of Patent: February 2, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Aarul Jain, Neha Agarwal, Rakesh Pandey, Deboleena Minz Sakalley
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Patent number: 8886874Abstract: A system for operating a flash memory includes a memory controller in communication with a processor. The memory controller includes a memory read access command receiver that receives a memory read access command from the processor. The memory read access command includes a memory cell address of a memory cell to be accessed for the execution of the memory read accessed command. The memory cell address includes a current sector address and a sector specific memory cell address. The flash memory is provided with either both the current sector address and the sector specific memory cell address or only the sector specific memory cell address for generating the memory cell address.Type: GrantFiled: June 24, 2013Date of Patent: November 11, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Deboleena Minz Sakalley, Rakesh Pandey
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Patent number: 8140738Abstract: A memory interface module provides interfacing between a host processor with multiple flash memories and parallel interfaces of varying protocols. The interface module includes multiple register files, multiple operation information registers, an internal memory, a flash interface portion, and a finite state machine (FSM). The register files receive a command from the host processor for controlling an operation of multiple flash memories. The operation information registers execute and store the command and operation information. The internal memory receives and stores host data from the host processor. The internal memory further stores flash data extracted from multiple flash memories. The flash interface portion interacts with the memory devices connected to the controller. The FSM extracts the command and the operation information from the register files, which are programmed by the user and controls the control signals of the memory devices connected to the controller through the flash interface.Type: GrantFiled: July 19, 2007Date of Patent: March 20, 2012Assignee: STMicroelectronics Pvt. Ltd.Inventors: Deboleena Minz, Sanjeev Varshney
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Patent number: 8112466Abstract: An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a highly compact manner. A novel method for cascading these blocks with the help of dedicated DSP lines is provided, which leads to a very simple and proficient implementation of n-stage MAC operations.Type: GrantFiled: September 28, 2005Date of Patent: February 7, 2012Assignee: Sicronic Remote KG, LLCInventors: Deboleena Minz, Kailash Digari
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Patent number: 7961004Abstract: A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.Type: GrantFiled: December 22, 2009Date of Patent: June 14, 2011Assignee: Sicronic Remote KG, LLCInventors: Deboleena Minz, Kailash Digari
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Patent number: 7755387Abstract: An improved FPGA having a direct interconnect structure to provide selective data routing without stressing the general-purpose routing resources and to enable high rate of data exchange within the FPGA. At least two IP cores are connected to each other through the direct interconnect structure to enable simultaneous data interaction among the ports of the IP cores and to provide configurable bus width routing between the IP cores, and a plurality of logic blocks connected to the IP cores through the direct interconnect structure to enable simultaneous data routing among the IP cores and the plurality of logic blocks.Type: GrantFiled: November 1, 2005Date of Patent: July 13, 2010Assignee: Sicronic Remote KG, LLCInventors: Deboleena Minz, Kailash Digari
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Publication number: 20100097099Abstract: A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.Type: ApplicationFiled: December 22, 2009Publication date: April 22, 2010Inventors: Deboleena Minz, Kailash Digari
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Patent number: 7475105Abstract: A one bit full adder with sum and carry outputs performs independent functions. The full adder includes at least one look up table (LUT) for implementing a sum function, and at least one carry circuit for implementing a carry/borrow function. The carry circuit includes a first multiplexer having first and second inputs, a select line input, and a carry/borrow output. The carry circuit also includes an AND gate, an OR gate and an XOR gate. The AND gate has two inputs, and an output connected to the first input of the first multiplexer. The OR gate has two inputs, and an output connected to the second input of the first multiplexer. The XOR gate has a first input, and an output connected to the select line input of the first multiplexer. A second multiplexer has an output connected to the first input of the XOR gate. The at least one LUT and the at least one carry circuit provides independent sum and carry outputs for different function requirements.Type: GrantFiled: June 15, 2005Date of Patent: January 6, 2009Assignee: STMicroelectronics Pvt. Ltd.Inventor: Deboleena Minz
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Publication number: 20080052448Abstract: A memory interface module provides interfacing between a host processor with multiple flash memories and parallel interfaces of varying protocols. The interface module includes multiple register files, multiple operation information registers, an internal memory, a flash interface portion, and a finite state machine (FSM). The register files receive a command from the host processor for controlling an operation of multiple flash memories. The operation information registers execute and store the command and operation information. The internal memory receives and stores host data from the host processor. The internal memory further stores flash data extracted from multiple flash memories. The flash interface portion interacts with the memory devices connected to the controller. The FSM extracts the command and the operation information from the register files, which are programmed by the user and controls the control signals of the memory devices connected to the controller through the flash interface.Type: ApplicationFiled: July 19, 2007Publication date: February 28, 2008Applicant: STMicroelectronics PVT. LTD.Inventors: Deboleena Minz, Sanjeev Varshney
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Publication number: 20060119388Abstract: An improved FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.Type: ApplicationFiled: November 1, 2005Publication date: June 8, 2006Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Deboleena Minz, Kailash Digari
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Publication number: 20060075012Abstract: An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a highly compact manner. A novel method for cascading these blocks with the help of dedicated DSP lines is provided, which leads to a very simple and proficient implementation of n-stage MAC operations.Type: ApplicationFiled: September 28, 2005Publication date: April 6, 2006Applicant: STMicroelectronics Pvt. Ltd.Inventors: Deboleena Minz, Kailash Digari
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Publication number: 20050289211Abstract: A one bit full adder with sum and carry outputs performs independent functions. The full adder includes at least one look up table (LUT) for implementing a sum function, and at least one carry circuit for implementing a carry/borrow function. The carry circuit includes a first multiplexer having first and second inputs, a select line input, and a carry/borrow output. The carry circuit also includes an AND gate, an OR gate and an XOR gate. The AND gate has two inputs, and an output connected to the first input of the first multiplexer. The OR gate has two inputs, and an output connected to the second input of the first multiplexer. The XOR gate has a first input, and an output connected to the select line input of the first multiplexer. A second multiplexer has an output connected to the first input of the XOR gate. The at least one LUT and the at least one carry circuit provides independent sum and carry outputs for different function requirements.Type: ApplicationFiled: June 15, 2005Publication date: December 29, 2005Applicant: STMicroelectronics Pvt.Ltd.Inventor: Deboleena Minz