Patents by Inventor Deborah A. Leek

Deborah A. Leek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7079966
    Abstract: A method of qualifying a process tool includes steps of: (a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer; (b) subjecting the semiconductor wafer to processing by the process tool; (c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer; and (d) calculating a plurality of defect locations added by the process tool from the pre-scan defect locations and the post-scan defect locations.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: July 18, 2006
    Assignee: LSI Logic Corporation
    Inventors: John A. Knoch, Deborah A. Leek, Nathan Strader
  • Publication number: 20060069659
    Abstract: A method of determining a cost effective number of corrective tests to perform on a process experiencing process excursions. A test cost for each corrective test is determined, and a total test cost for each of an incremental number of corrective tests is calculated. An effect of each corrective test on a reduction in the process excursions is determined, as is also the lost revenue for each process excursion. A reduction in the lost revenue for each of the incremental number of corrective tests is calculated, based at least in part on the effect of each corrective test on the reduction in process excursions and the revenue lost for each process excursion. An overall cost for each of the incremental number of corrective tests is calculated, based at least in part on a sum of the total test cost and the reduction in the lost revenue for each of the incremental number of corrective tests.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 30, 2006
    Inventors: Michael Gatov, Deborah Leek, Bruce Whitefield
  • Publication number: 20050065739
    Abstract: A method of qualifying a process tool includes steps of: (a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer; (b) subjecting the semiconductor wafer to processing by the process tool; (c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer; and (d) calculating a plurality of defect locations added by the process tool from the pre-scan defect locations and the post-scan defect locations.
    Type: Application
    Filed: September 8, 2003
    Publication date: March 24, 2005
    Inventors: John Knoch, Deborah Leek, Nathan Strader