Patents by Inventor Deborah COGONI
Deborah COGONI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12627024Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.Type: GrantFiled: December 19, 2023Date of Patent: May 12, 2026Assignee: STMicroelectronics (Alps) SASInventor: Deborah Cogoni
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Publication number: 20260094973Abstract: A laminate substrate for a radio frequency device successively includes: a first metal layer, in which is formed a first slot open at least partially on one of its sides, with a feed line extending into the first slot; a second metal layer in which is formed a second laterally closed slot; a third metal layer in which is formed a third laterally closed slot; a fourth metal layer in which is formed a fourth laterally closed slot, connection pads being bonded to the fourth metal layer; the second slot, the third slot, and the fourth slot forming a vertical RF feedthrough; and a metal plate being positioned in the fourth slot.Type: ApplicationFiled: September 29, 2025Publication date: April 2, 2026Applicant: STMicroelectronics International N.V.Inventors: Vipin VELAYUDHAN, Deborah COGONI
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Publication number: 20260068679Abstract: Semiconductor device includes an integrated circuit package having a connection array for a connection to a printed circuit. The integrated circuit package includes a shield structure against electromagnetic interference from elementary connectors, such as balls. The shield structure is formed by deposition by 3D printing of a metal shield wall between the elementary connectors.Type: ApplicationFiled: August 19, 2025Publication date: March 5, 2026Applicant: STMicroelectronics International N.V.Inventors: Deborah COGONI, Vipin VELAYUDHAN
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Publication number: 20250240871Abstract: A laminated structure includes metal tracks. In a method for making, a first layer of a first dielectric material is deposited on a substrate. One or more openings are then made in the first layer. A second dielectric material is then deposited within the openings formed in the first layer. The second dielectric material has dielectric properties distinct from the dielectric properties of the first dielectric material.Type: ApplicationFiled: January 15, 2025Publication date: July 24, 2025Applicant: STMicroelectronics International N.V.Inventors: Deborah COGONI, Claire LAPORTE, David AUCHERE, Laurent SCHWARTZ
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Patent number: 12292607Abstract: An optical package includes a substrate made of a first material having an upper surface and a lower surface. The substrate further includes at least one cavity opening onto an upper surface of the substrate. Electrical connection vias extend through the substrate. An electronic integrated circuit chip is mounted on the upper surface of the substrate in a position so as to cover the at least one cavity. The electronic integrated circuit chip includes an integrated optical sensor. Each cavity is filled with a second material having a thermal conductivity greater than the thermal conductivity of the first material. The electrical connection vias are arranged on either side of each cavity and between two cavities.Type: GrantFiled: May 3, 2022Date of Patent: May 6, 2025Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SASInventors: Deborah Cogoni, Raphael Goubot, Younes Boutaleb
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Patent number: 12051681Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.Type: GrantFiled: July 13, 2021Date of Patent: July 30, 2024Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ALPS) SASInventors: Deborah Cogoni, David Auchere, Laurent Schwartz, Claire Laporte
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Publication number: 20240120638Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Applicant: STMicroelectronics (Alps) SASInventor: Deborah COGONI
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Patent number: 11888208Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.Type: GrantFiled: August 23, 2021Date of Patent: January 30, 2024Assignee: STMicroelectronics (Alps) SASInventor: Deborah Cogoni
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Patent number: 11756874Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.Type: GrantFiled: September 15, 2022Date of Patent: September 12, 2023Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: David Auchere, Claire Laporte, Deborah Cogoni, Laurent Schwartz
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Publication number: 20230015669Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.Type: ApplicationFiled: September 15, 2022Publication date: January 19, 2023Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: David AUCHERE, Claire LAPORTE, Deborah COGONI, Laurent SCHWARTZ
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Publication number: 20220357536Abstract: An optical package includes a substrate made of a first material having an upper surface and a lower surface. The substrate further includes at least one cavity opening onto an upper surface of the substrate. Electrical connection vias extend through the substrate. An electronic integrated circuit chip is mounted on the upper surface of the substrate in a position so as to cover the at least one cavity. The electronic integrated circuit chip includes an integrated optical sensor. Each cavity is filled with a second material having a thermal conductivity greater than the thermal conductivity of the first material. The electrical connection vias are arranged on either side of each cavity and between two cavities.Type: ApplicationFiled: May 3, 2022Publication date: November 10, 2022Applicants: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SASInventors: Deborah COGONI, Raphael GOUBOT, Younes BOUTALEB
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Patent number: 11482487Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.Type: GrantFiled: October 6, 2020Date of Patent: October 25, 2022Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: David Auchere, Claire Laporte, Deborah Cogoni, Laurent Schwartz
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Publication number: 20220069430Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.Type: ApplicationFiled: August 23, 2021Publication date: March 3, 2022Applicant: STMicroelectronics (Alps) SASInventor: Deborah COGONI
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Publication number: 20220028844Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.Type: ApplicationFiled: July 13, 2021Publication date: January 27, 2022Applicants: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ALPS) SASInventors: Deborah COGONI, David AUCHERE, Laurent SCHWARTZ, Claire Laporte
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Publication number: 20210104457Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.Type: ApplicationFiled: October 6, 2020Publication date: April 8, 2021Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: David AUCHERE, Claire LAPORTE, Deborah COGONI, Laurent SCHWARTZ
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Patent number: 10811349Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.Type: GrantFiled: August 23, 2018Date of Patent: October 20, 2020Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: David Auchere, Laurent Schwarz, Deborah Cogoni, Eric Saugier
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Publication number: 20190067180Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.Type: ApplicationFiled: August 23, 2018Publication date: February 28, 2019Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: David AUCHERE, Laurent SCHWARZ, Deborah COGONI, Eric SAUGIER