Patents by Inventor Deborah COGONI

Deborah COGONI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12627024
    Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: May 12, 2026
    Assignee: STMicroelectronics (Alps) SAS
    Inventor: Deborah Cogoni
  • Publication number: 20260094973
    Abstract: A laminate substrate for a radio frequency device successively includes: a first metal layer, in which is formed a first slot open at least partially on one of its sides, with a feed line extending into the first slot; a second metal layer in which is formed a second laterally closed slot; a third metal layer in which is formed a third laterally closed slot; a fourth metal layer in which is formed a fourth laterally closed slot, connection pads being bonded to the fourth metal layer; the second slot, the third slot, and the fourth slot forming a vertical RF feedthrough; and a metal plate being positioned in the fourth slot.
    Type: Application
    Filed: September 29, 2025
    Publication date: April 2, 2026
    Applicant: STMicroelectronics International N.V.
    Inventors: Vipin VELAYUDHAN, Deborah COGONI
  • Publication number: 20260068679
    Abstract: Semiconductor device includes an integrated circuit package having a connection array for a connection to a printed circuit. The integrated circuit package includes a shield structure against electromagnetic interference from elementary connectors, such as balls. The shield structure is formed by deposition by 3D printing of a metal shield wall between the elementary connectors.
    Type: Application
    Filed: August 19, 2025
    Publication date: March 5, 2026
    Applicant: STMicroelectronics International N.V.
    Inventors: Deborah COGONI, Vipin VELAYUDHAN
  • Publication number: 20250240871
    Abstract: A laminated structure includes metal tracks. In a method for making, a first layer of a first dielectric material is deposited on a substrate. One or more openings are then made in the first layer. A second dielectric material is then deposited within the openings formed in the first layer. The second dielectric material has dielectric properties distinct from the dielectric properties of the first dielectric material.
    Type: Application
    Filed: January 15, 2025
    Publication date: July 24, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Deborah COGONI, Claire LAPORTE, David AUCHERE, Laurent SCHWARTZ
  • Patent number: 12292607
    Abstract: An optical package includes a substrate made of a first material having an upper surface and a lower surface. The substrate further includes at least one cavity opening onto an upper surface of the substrate. Electrical connection vias extend through the substrate. An electronic integrated circuit chip is mounted on the upper surface of the substrate in a position so as to cover the at least one cavity. The electronic integrated circuit chip includes an integrated optical sensor. Each cavity is filled with a second material having a thermal conductivity greater than the thermal conductivity of the first material. The electrical connection vias are arranged on either side of each cavity and between two cavities.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: May 6, 2025
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Deborah Cogoni, Raphael Goubot, Younes Boutaleb
  • Patent number: 12051681
    Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: July 30, 2024
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ALPS) SAS
    Inventors: Deborah Cogoni, David Auchere, Laurent Schwartz, Claire Laporte
  • Publication number: 20240120638
    Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Applicant: STMicroelectronics (Alps) SAS
    Inventor: Deborah COGONI
  • Patent number: 11888208
    Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: January 30, 2024
    Assignee: STMicroelectronics (Alps) SAS
    Inventor: Deborah Cogoni
  • Patent number: 11756874
    Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: September 12, 2023
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: David Auchere, Claire Laporte, Deborah Cogoni, Laurent Schwartz
  • Publication number: 20230015669
    Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 19, 2023
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: David AUCHERE, Claire LAPORTE, Deborah COGONI, Laurent SCHWARTZ
  • Publication number: 20220357536
    Abstract: An optical package includes a substrate made of a first material having an upper surface and a lower surface. The substrate further includes at least one cavity opening onto an upper surface of the substrate. Electrical connection vias extend through the substrate. An electronic integrated circuit chip is mounted on the upper surface of the substrate in a position so as to cover the at least one cavity. The electronic integrated circuit chip includes an integrated optical sensor. Each cavity is filled with a second material having a thermal conductivity greater than the thermal conductivity of the first material. The electrical connection vias are arranged on either side of each cavity and between two cavities.
    Type: Application
    Filed: May 3, 2022
    Publication date: November 10, 2022
    Applicants: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Deborah COGONI, Raphael GOUBOT, Younes BOUTALEB
  • Patent number: 11482487
    Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: October 25, 2022
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: David Auchere, Claire Laporte, Deborah Cogoni, Laurent Schwartz
  • Publication number: 20220069430
    Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.
    Type: Application
    Filed: August 23, 2021
    Publication date: March 3, 2022
    Applicant: STMicroelectronics (Alps) SAS
    Inventor: Deborah COGONI
  • Publication number: 20220028844
    Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 27, 2022
    Applicants: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ALPS) SAS
    Inventors: Deborah COGONI, David AUCHERE, Laurent SCHWARTZ, Claire Laporte
  • Publication number: 20210104457
    Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.
    Type: Application
    Filed: October 6, 2020
    Publication date: April 8, 2021
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: David AUCHERE, Claire LAPORTE, Deborah COGONI, Laurent SCHWARTZ
  • Patent number: 10811349
    Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 20, 2020
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: David Auchere, Laurent Schwarz, Deborah Cogoni, Eric Saugier
  • Publication number: 20190067180
    Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 28, 2019
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: David AUCHERE, Laurent SCHWARZ, Deborah COGONI, Eric SAUGIER