Abstract: Various implementations include systems and methods for simultaneously applying an electric field and localized energy from an energy source to ceramic particles on a layer by layer basis to form a ceramic workpiece using additive manufacturing. The workpiece may be freely removed from the unsintered ceramic particles. In some implementations, the workpiece is partially densified when removed from the unsintered ceramic particles, but it may be heated until fully densified. According to some implementations, these systems and methods remove or reduce the need for binders and reduce manufacturing time.

Abstract: Various implementations include systems and methods for simultaneously applying an electric field and localized energy from an energy source to ceramic particles on a layer by layer basis to form a ceramic workpiece using additive manufacturing. The workpiece may be freely removed from the unsintered ceramic particles. In some implementations, the workpiece is partially densified when removed from the unsintered ceramic particles, but it may be heated until fully densified. According to some implementations, these systems and methods remove or reduce the need for binders and reduce manufacturing time.

Abstract: A semiconductor package substrate (11) has an array of package sites (13, 14, 16, and 21) that are substantially identical. The entire array of package sites (13, 14, 16, and 21) is covered by an encapsulant (19). The individual package sites (13, 14, 16, and 21) are singulated by sawing through the encapsulant (19) and the underlying semiconductor package substrate (11).

Abstract: A system (10) is disclosed having a circuit portion (18,26,36) containing more than electrical conductors and a wirebonded assemblage (12,14,16) overlying the circuit portion (18,26,36). The wirebonded assemblage (12,14,16) comprises a plurality of wirebonded wires ((50,52),(60,64),(66,68)), each of the plurality of wirebonded wires being electrically coupled. The wirebonded assemblage (12,14,16) provides electrical shielding for the circuit portion (18,26,36). In one embodiment, the wirebonded assemblage provides for heat spreading.

Abstract: A system (10) is disclosed having a circuit portion (18,26,36) containing more than electrical conductors and a wirebonded assemblage (12,14,16) overlying the circuit portion (18,26,36). The wirebonded assemblage (12,14,16) comprises a plurality of wirebonded wires ((50,52),(60,64),(66,68)), each of the plurality of wirebonded wires being electrically coupled. The wirebonded assemblage (12,14,16) provides electrical shielding for the circuit portion (18,26,36). In one embodiment, the wirebonded assemblage provides for heat spreading.

Abstract: An interconnect structure, such as a flip-chip structure, including a base pad and a stud formed on the base pad and extending from the base pad is disclosed. The stud and base pad are formed to be continuous and of substantially the same electrically conductive base material. Typically, a solder structure is formed on the stud wherein the solder structure is exposed for subsequent reflow attachment to another structure. The present invention relates to packaging integrated circuits, more particularly to the structure and processing of a stud and bump without the standard under bump metallurgy.

Abstract: A semiconductor package substrate (10) has an array of package sites (13,14,16,21,22, and 23) that are substantially identical. The entire array of package sites (13,14,16,21,22, and 23) is covered by an encapsulant (19). The individual package sites (13,14,16,21,22, and 23) are singulated by sawing through the encapsulant (19) and the underlying semiconductor package substrate (10).

Abstract: A semiconductor package substrate (10) has an array of package sites (13,14,16,21,22, and 23) that are substantially identical. The entire array of package sites (13,14,16,21,22, and 23) is covered by an encapsulant (19). The individual package sites (13,14,16,21,22, and 23) are singulated by sawing through the encapsulant (19) and the underlying semiconductor package substrate (10).