Patents by Inventor Deborah J. Riley

Deborah J. Riley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7569464
    Abstract: The present invention provides a method for manufacturing a semiconductor device, which includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 4, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Karen H. R. Kirmse, Yuanning Chen, Jarvis B. Jacobs, Deborah J. Riley
  • Patent number: 7537988
    Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: May 26, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Shashank Ekbote, Deborah J. Riley, Borna Obradovic
  • Publication number: 20090098695
    Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted.
    Type: Application
    Filed: October 10, 2007
    Publication date: April 16, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Shashank Ekbote, Deborah J. Riley, Borna Obradovic
  • Patent number: 7422969
    Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: September 9, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio L. P. Rotondaro, Deborah J. Riley, Trace Q. Hurd
  • Publication number: 20080153273
    Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, in one embodiment, includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Karen H.R. Kirmse, Yuanning Chen, Jarvis B. Jacobs, Deborah J. Riley
  • Patent number: 7384869
    Abstract: A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed portion from etching by phosphoric acid. The method can include exposing the silicon to at least one of a hot ozonated sulfuric acid and a hot peroxide sulfuric acid to form the thick chemical oxide.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: June 10, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Deborah J. Riley, Brian M. Trentman, Brian K. Kirkpatrick
  • Patent number: 7371691
    Abstract: The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 and cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layer 270 to a plasma ash. The plasma ash removes at least a portion of a crust 275 formed on the photoresist layer 270 but leaves a substantial portion of the photoresist layer 270. The photoresist layer 270 is subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer 270.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: May 13, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Lindsey H. Hall, Trace Q. Hurd, Deborah J. Riley
  • Patent number: 7323403
    Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: January 29, 2008
    Assignee: Texas Instruments Incroporated
    Inventors: Antonio L. P. Rotondaro, Deborah J. Riley, Trace Q. Hurd
  • Patent number: 7132365
    Abstract: A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non-thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: November 7, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Sue Ellen Crank, Shirin Siddiqui, Deborah J. Riley, Trace Quentin Hurd, Peijun J. Chen
  • Patent number: 7098099
    Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: August 29, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Brian E. Hornung, Jong Yoon, Deborah J. Riley, Amitava Chatterjee
  • Patent number: 6492275
    Abstract: Methods of patterning sidewall spacers are provided. In one aspect, a method of fabricating a circuit device includes forming a gate on a substrate and forming a first oxide spacer and a second oxide spacer adjacent to the gate. The width of the gate and the first and second oxide spacers is measured. The widths of the first and second oxide spacers are trimmed if the width of the gate and the first and second oxide spacers exceeds a preselected maximum value by exposing the first and second oxide spacers to a solution of ammonium hydroxide, hydrogen peroxide and water for a preselected like and rinsing with deionized water. Spacer width may be finely tuned to reduce the risk of weak overlap and to improve device characteristics through shorter channels.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: December 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Deborah J. Riley, Terri A. Couteau
  • Publication number: 20020119647
    Abstract: Methods of patterning sidewall spacers are provided. In one aspect, a method of fabricating a circuit device includes forming a gate on a substrate and forming a first oxide spacer and a second oxide spacer adjacent to the gate. The width of the gate and the first and second oxide spacers is measured. The widths of the first and second oxide spacers are trimmed if the width of the gate and the first and second oxide spacers exceeds a preselected maximum value by exposing the first and second oxide spacers to a solution of NH4OH, H2O2 and H2O for a preselected time and rinsing with deionized water. Spacer width may be finely tuned to reduce the risk of weak overlap and to improve device characteristics through shorter channels.
    Type: Application
    Filed: January 21, 2000
    Publication date: August 29, 2002
    Inventors: Deborah J Riley, Terri A Couteau