Patents by Inventor Deborah Tibel

Deborah Tibel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for accelerated determination of electromigration characteristics of semiconductor wiring
    Patent number: 6603321
    Abstract: A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: August 5, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Jr., Alvin W. Strong, Timothy D. Sullivan, Deborah Tibel, Michael Ruprecht, Carole Graas
  • METHOD AND APPARATUS FOR ACCELERATED DETERMINATION OF ELECTROMIGRATION CHARACTERISTICS OF SEMICONDUCTOR WIRING
    Publication number: 20030080761
    Abstract: A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type.
    Type: Application
    Filed: October 26, 2001
    Publication date: May 1, 2003
    Applicant: International Business Machines Corporation and Infineon Technologies North America Corp.
    Inventors: Ronald G. Filippi, Alvin W. Strong, Timothy D. Sullivan, Deborah Tibel, Michael Ruprecht, Carole Graas