Patents by Inventor Debra Bernstein
Debra Bernstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220113967Abstract: A system comprising a discrete graphics system-on-chip (SoC) to couple to a host processor unit, the SoC comprising a fabric comprising a handler circuitry to decode a request from a compute engine, the handler circuitry to route the request based on an opcode included in the request, the handler configured to decode the opcode from a set of opcodes for use in requests by the compute engine, wherein the set of opcodes include opcodes corresponding to a first write request type and a first read request type, wherein requests of the first write request type and the first read request type are routed to either the host memory or the graphics memory; and a second write request type and a second read request type, wherein requests of the second write request type and the second request type are to be routed to the sideband network.Type: ApplicationFiled: December 23, 2021Publication date: April 14, 2022Applicant: Intel CorporationInventors: Abhishek Reddy Pamu, Lakshminarayana Pappu, David J. Harriman, Debra Bernstein, Ramadass Nagarajan
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Patent number: 11134021Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.Type: GrantFiled: December 29, 2016Date of Patent: September 28, 2021Assignee: INTEL CORPORATIONInventors: Jonathan Kenny, Niall D. McDonnell, Andrew Cunningham, Debra Bernstein, William G. Burroughs, Hugh Wilkinson
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Publication number: 20210200667Abstract: Examples described herein relate to memory thin provisioning in a memory pool of one or more dual in-line memory modules or memory devices. At any instance, any central processing unit (CPU) can request and receive a full virtual allocation of memory in an amount that exceeds the physical memory attached to the CPU (near memory). A remote pool of additional memory can be dynamically utilized to fill the gap between allocated memory and near memory. This remote pool is shared between multiple CPUs, with dynamic assignment and address re-mapping provided for the remote pool. To improve performance, the near memory can be operated as a cache of the pool memory. Inclusive or exclusive content storage configurations can be applied. An inclusive cache configuration can include an entry in a near memory cache also being stored in a memory pool whereas an exclusive cache configuration can provide an entry in either a near memory cache or in a memory pool but not both.Type: ApplicationFiled: December 26, 2019Publication date: July 1, 2021Inventors: Debra BERNSTEIN, Hugh WILKINSON, Douglas CARRIGAN, Bassam N. COURY, Matthew J. ADILETTA, Durgesh SRIVASTAVA, Lidia WARNES, William WHEELER, Michael F. FALLON
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Publication number: 20210117242Abstract: Examples described herein relate to an Infrastructure Processing Unit (IPU) that comprises: interface circuitry to provide a communicative coupling with a platform; network interface circuitry to provide a communicative coupling with a network medium; and circuitry to expose infrastructure services to be accessed by microservices for function composition.Type: ApplicationFiled: December 26, 2020Publication date: April 22, 2021Inventors: Johan VAN DE GROENENDAAL, Kshitij A. DOSHI, Edmund CHEN, Ravi SAHITA, Andrew J. HERDRICH, Debra BERNSTEIN, Christine E. SEVERNS-WILLIAMS, Uri V. CUMMINGS, Utkarsh Y. KAKAIYA
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Publication number: 20210117249Abstract: Examples described herein relate to an Infrastructure Processing Unit (IPU) that comprises: interface circuitry to provide a communicative coupling with a platform; network interface circuitry to provide a communicative coupling with a network medium; and circuitry to expose infrastructure services to be accessed by microservices for function composition and to selectively provide a barrier to halt operation of at least one microservice based on event data from a composite node that performs the at least one microservice.Type: ApplicationFiled: December 26, 2020Publication date: April 22, 2021Inventors: Kshitij A. DOSHI, Johan VAN DE GROENENDAAL, Edmund CHEN, Ravi SAHITA, Andrew J. HERDRICH, Debra BERNSTEIN, Christine E. SEVERNS-WILLIAMS, Uri V. CUMMINGS, Utkarsh Y. KAKAIYA
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Patent number: 10929323Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.Type: GrantFiled: October 14, 2019Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Ren Wang, Yipeng Wang, Andrew Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai, Niall D. McDonnell, Hugh Wilkinson, Bradley A. Burres, Bruce Richardson, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren, An Yan, Andrew Cunningham, David Sonnier, Gage Eads, James T. Clee, Jamison D. Whitesell, Jerry Pirog, Jonathan Kenny, Joseph R. Hasting, Narender Vangati, Stephen Miller, Te K. Ma, William Burroughs
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Patent number: 10761979Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.Type: GrantFiled: July 1, 2016Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Hugh Wilkinson, William R. Wheeler, Debra Bernstein
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Publication number: 20200042479Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.Type: ApplicationFiled: October 14, 2019Publication date: February 6, 2020Applicant: Intel CorporationInventors: Ren Wang, Yipeng Wang, Andrew Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai, Niall D. McDonnell, Hugh Wilkinson, Bradley A. Burres, Bruce Richardson, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren, An Yan, Andrew Cunningham, David Sonnier, Gage Eads, James T. Clee, Jamison D. Whitesell, Jerry Pirog, Jonathan Kenny, Joseph R. Hasting, Narender Vangati, Stephen Miller, Te K. Ma, William Burroughs
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Patent number: 10445271Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.Type: GrantFiled: January 4, 2016Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Ren Wang, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren, An Yan, Andrew Cunningham, David Sonnier, Gage Eads, James T. Clee, Jamison D. Whitesell, Yipeng Wang, Jerry Pirog, Jonathan Kenny, Joseph R. Hasting, Narender Vangati, Stephen Miller, Te K. Ma, William Burroughs, Andrew J. Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai, Niall D. McDonnell, Hugh Wilkinson, Bradley A. Burres, Bruce Richardson
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Patent number: 10216668Abstract: Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.Type: GrantFiled: March 31, 2016Date of Patent: February 26, 2019Assignee: Intel CorporationInventors: Ren Wang, Yipeng Wang, Jr-Shian Tsai, Andrew Herdrich, Tsung-Yuan Tai, Niall McDonnell, Stephen Van Doren, David Sonnier, Debra Bernstein, Hugh Wilkinson, Narender Vangati, Stephen Miller, Gage Eads, Andrew Cunningham, Jonathan Kenny, Bruce Richardson, William Burroughs, Joseph Hasting, An Yan, James Clee, Te Ma, Jerry Pirog, Jamison Whitesell
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Publication number: 20190042305Abstract: Technologies for moving workloads between hardware queue managers include a compute device. The compute device includes a set of hardware queue managers. Each hardware queue manager is to manage one or more queues of queue elements and each queue element is indicative of a data set to be operated on by a thread. The compute device also includes circuitry to execute a workload with a first hardware queue manager of the set of hardware queue managers, determine whether a workload migration condition is present, determine whether a second hardware queue manager of the set of hardware queue managers has sufficient capacity to manage a set of queues associated with the workload, move, in response to a determination that the second hardware queue manager does have sufficient capacity, the workload to the second hardware queue manager, and reduce, after the move of the workload to the second hardware queue manager, a power usage of the first hardware queue manager.Type: ApplicationFiled: March 6, 2018Publication date: February 7, 2019Inventors: Niall D. McDonnell, Debra Bernstein, Patrick Fleming, Chris Macnamara, Andrew Cunningham, Bruce Richardson, Brendan N. Ryan
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Publication number: 20180191630Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Applicant: INTEL CORPORATIONInventors: JONATHAN KENNY, NIALL D. MCDONNELL, ANDREW CUNNINGHAM, DEBRA BERNSTEIN, WILLIAM G. BURROUGHS, HUGH WILKINSON
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Publication number: 20180004655Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.Type: ApplicationFiled: July 1, 2016Publication date: January 4, 2018Applicant: Intel CorporationInventors: Hugh Wilkinson, William R. Wheeler, Debra Bernstein
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Patent number: 9830285Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: GrantFiled: October 14, 2015Date of Patent: November 28, 2017Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 9830284Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: GrantFiled: July 27, 2015Date of Patent: November 28, 2017Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 9824038Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: GrantFiled: October 14, 2015Date of Patent: November 21, 2017Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 9824037Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: GrantFiled: October 14, 2015Date of Patent: November 21, 2017Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Publication number: 20170286337Abstract: Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: Ren Wang, Yipeng Wang, Jr-Shian Tsai, Andrew Herdrich, Tsung-Yuan Tai, Niall McDonnell, Stephen Van Doren, David Sonnier, Debra Bernstein, Hugh Wilkinson, Narender Vangati, Stephen Miller, Gage Eads, Andrew Cunningham, Jonathan Kenny, Bruce Richardson, William Burroughs, Joseph Hasting, An Yan, James Clee, Te Ma, Jerry Pirog, Jamison Whitesell
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Publication number: 20170192921Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.Type: ApplicationFiled: January 4, 2016Publication date: July 6, 2017Inventors: Ren Wang, Yipeng Wang, Andrew J. Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai, Niall D. McDonnell, Hugh Wilkinson, Bradley A. Burres, Bruce Richardson, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren, An Yan, Andrew Cunningham, David Sonnier, Gage Eads, James T. Clee, Jamison D. Whitesell, Jerry Pirog, Jonathan Kenny, Joseph R. Hasting, Narender Vangati, Stephen Miller, Te K. Ma, William Burroughs
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Patent number: 9535860Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.Type: GrantFiled: January 17, 2013Date of Patent: January 3, 2017Assignee: Intel CorporationInventors: Daniel F. Cutter, Blaise Fanning, Ramadass Nagarajan, Jose S. Niell, Debra Bernstein, Deepak Limaye, Ioannis T. Schoinas, Ravishankar Iyer