Patents by Inventor Debra Dean

Debra Dean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240119205
    Abstract: A computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. An analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. A stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. Such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and/or multi-cycle violation of the digital integrated circuit. A design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. In this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and/or multi-cycle violations using a rules-based approach.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: SheshaShayee K Raghunathan, Charles Gates, Kerim Kalafala, Steven Joseph Kurtz, Morgan D. Davis, Debra Dean, Chris Cavitt, Chaitra M Bhat, Richard William Taggart
  • Patent number: 10891412
    Abstract: An electronic design automation (EDA) data processing system includes a version graph database and a controller. The version graph database stores a plurality of different versions of graph data sets. Each graph data set corresponds to a respective circuit component located at a given hierarchical level of a semiconductor chip design and each graph data set tagged with a version identifier (ID) indicating the version thereof. The controller determines a hierarchical circuit included in the semiconductor chip and determines a plurality of targeted circuit components that define the hierarchical circuit. The controller determines targeted graph data sets from the versions graph database that correspond to the targeted circuit components, and obtains the targeted graph data sets having matching version IDs such that the targeted graph data sets are the same version.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sheshashayee K. Raghunathan, Thomas S. Guzowski, Nathan Buck, Kerim Kalafala, Jack DiLullo, Debra Dean
  • Patent number: RE49910
    Abstract: An apparatus and method for locking a detonating cord against a shaped charge.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: April 9, 2024
    Assignee: Hunting Titan, Inc.
    Inventors: William Richard Collins, Debra Christine McDonald, Bradley Dean Schulte