Patents by Inventor Debra K. Gould

Debra K. Gould has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Capacitor constructions and methods of forming
    Patent number: 7440255
    Abstract: A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the layer. Alternatively, or additionally, the first electrode may contain Si and the layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. The layer may be a nitride layer and may be conductive or insulative. When conductive, the layer may exhibit a first conductivity greater than a second conductivity of the first electrode. The capacitor construction may be used in memory devices.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: October 21, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Brent A. McClure, Casey R. Kurth, Shenlin Chen, Debra K. Gould, Lyle D. Breiner, Er-Xuan Ping, Fred D. Fishburn, Hongmei Wang
  • High selective nitride etch
    Patent number: 5387312
    Abstract: A cleaner, selective etch process wherein NF.sub.3 ions and nitrogen ions are employed to bombard a patterned nitride layer disposed superjacent an oxide layer, thereby creating substantially vertical sidewalls, especially useful when etching submicron features.
    Type: Grant
    Filed: July 9, 1993
    Date of Patent: February 7, 1995
    Assignee: Micron Semiconductor, Inc.
    Inventors: David J. Keller, Debra K. Gould
  • Method for enhancing etch uniformity useful in etching submicron nitride features
    Patent number: 5338395
    Abstract: An etch process wherein halogen ions are employed to bombard a patterned nitride layer thereby creating substantially vertical sidewalls, especially useful when etching submicron features.A process in which NF.sub.3 ions are combined with halogen ions in a reactive ion etcher to etch a patterned layer, followed, in situ, by an overetch of NF.sub.3 ions and an ionized hydrogen halide. An inert gas can be added to further increase the uniformity of the etch.
    Type: Grant
    Filed: March 10, 1993
    Date of Patent: August 16, 1994
    Assignee: Micron Semiconductor, Inc.
    Inventors: David J. Keller, Debra K. Gould