Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.

Abstract: An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa.

Abstract: An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

Abstract: Decoder circuits capable of decoding encoded ROM memory are provided. Embodiments provide several improvements over prior solutions which rely primarily on CMOS logic (e.g., inverters). For example, embodiments provide faster decoding by limiting the number of decoding stages to a single stage. Further, embodiments allow the use of partial swing (as opposed to full swing) on the bit lines, which results in significant power reduction. This, in turn, results in reduced amounts of capacitor discharges when reading the data.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

Abstract: Decoder circuits capable of decoding encoded ROM memory are provided. Embodiments provide several improvements over prior solutions which rely primarily on CMOS logic (e.g., inverters). For example, embodiments provide faster decoding by limiting the number of decoding stages to a single stage. Further, embodiments allow the use of partial swing (as opposed to full swing) on the bit lines, which results in significant power reduction. This, in turn, results in reduced amounts of capacitor discharges when reading the data.

Abstract: An improved Content Addressable Memory (CAM) architecture and method for operating the same is provided herein. The improved CAM architecture may generally include an array of memory cells arranged into rows and columns, where each row includes a number of memory cells configured for storing one word. In particular, the number of memory cells may be coupled to a plurality of local match lines which, when combined through a hierarchy of two or more logic gates, form a match line signal for the entire word. Dynamic logic is used within a compare portion of each memory cell to reduce the occurrence of functional failures. In addition, the improved method for operating the CAM reduces power consumption and peak current, and improves timing, by eliminating the need to restore the match line voltage to a preset voltage level before each new compare operation.

Abstract: Multiple matches of words in a content addressable memory are detected by identifying each match of the input word to a word in the memory, and generating a representation of a relationship OR (xi AND xj), where xi=x1, x2, . . . xN?1, xj?xi+1, xi+2, . . . xN, and x1, x2, . . . , xN are the compare results of the individual words in the memory to the input word. A representation of at least one match is identified by generating a representation of a relationship x1 OR x2 OR x3 OR . . . OR xN. The apparatus comprises a hierarchy of logic that carries a general match representation indicating at least one match between the input word and all of the memory words, and a multiple-match representation indicating multiple matches between the input word and the words in the memory.

Abstract: An improved Content Addressable Memory (CAM) architecture and method for operating the same is provided herein. The improved CAM architecture may generally include an array of memory cells arranged into rows and columns, where each row includes a number of memory cells configured for storing one word. In particular, the number of memory cells may be coupled to a plurality of local match lines which, when combined through a hierarchy of two or more logic gates, form a match line signal for the entire word. Dynamic logic is used within a compare portion of each memory cell to reduce the occurrence of functional failures. In addition, the improved method for operating the CAM reduces power consumption and peak current, and improves timing, by eliminating the need to restore the match line voltage to a preset voltage level before each new compare operation.

Abstract: Multiple matches of words in a content addressable memory are detected by identifying each match of the input word to a word in the memory, and generating a representation of a relationship OR(xi AND xj), where xi=x1, x2, . . . , xN-1, xj?xi+1, xi+2, . . . xN, and x1, x2, . . . , xN are the compare results of the individual words in the memory to the input word. A representation of at least one match is identified by generating a representation of a relationship x1 OR x2 OR x3 OR . . . OR xN. The apparatus comprises a hierarchy of logic that carries a general match representation indicating at least one match between the input word and all of the memory words, and a multiple-match representation indicating multiple matches between the input word and the words in the memory.