Abstract: A method and a device for forecasting an electric load, an electronic device, and a computer-readable storage medium are provided. The method includes: acquiring historical load data prior to a forecast date; generating a load sequence based on the historical load data; performing variational mode decomposition on the load sequence, to obtain multiple intrinsic mode components and a residual that are corresponding to the load sequence; and inputting the multiple intrinsic mode components and the residual into respective forecasting models, and determining a load value on the forecast date based on forecasting results of all the forecasting models. With the method and the device, the electronic device, and the computer-readable storage medium, the load sequence is decomposed based on the variational mode decomposition, so that more dimensional feature information in the load sequence can be mined. Moreover, the residual is also used as valid data.

Abstract: A thermal-runaway warning method, system, and terminal for a power station are provided. The method comprises: obtaining collected data of a battery module comprised in the power station, wherein the collected data comprises collected temperature values of the battery module collected by temperature measuring devices; normalizing the collected data to obtain a standard dataset; training a CNNLSTM-based temperature predicting model based on the standard dataset to obtain a trained CNNLSTM-based temperature predicting model; and obtaining a predicted temperature value of the battery module within an output time window based on the trained CNNLSTM-based temperature predicting model, and determining whether there is a risk of thermal runaway in the power station based on the predicted temperature value.

Abstract: A push-pull power amplifier (PA) includes a pair of P-type transistors, a pair of N-type transistors, and a splitter, wherein source terminals of the pair of P-type transistors are coupled to a first reference voltage, source terminals of the pair of N-type transistors are coupled to a second reference voltage, and drain terminals of the pair of P-type transistors and drain terminals of the pair of N-type transistors are coupled to an output port of the push-pull PA. The splitter is arranged to receive a common-mode input pair, and provide two differential output pairs to the pair of P-type transistors and the pair of N-type transistors, wherein one of the two differential output pairs is provided to gate terminals of the pair of P-type transistors, and the other of the two differential output pairs is provided to gate terminals of the pair of N-type transistors.

Abstract: A differential amplifier and a method thereof are described. The method, adopted by a differential amplifier, includes: generating first stage differential output signals based on input differential signals; providing, by a current source, a bias current with a desired quiescent current; biasing first and second control transistors with the bias current to generate first and second currents, respectively, wherein the first and second control transistors form a differential pair which receives first stage differential input signals; mirroring the first and second currents to first and second push transistors which are connected to first and second pull transistors in series, respectively; and biasing the first and second pull transistors with the mirrored first and second currents, respectively; wherein each pair of serial connected push and pull transistors are complimentary and the two pairs of push and pull transistors output second stage differential output signals.

Abstract: A differential amplifier and a method thereof are described. The method, adopted by a differential amplifier, includes: generating first stage differential output signals based on input differential signals; providing, by a current source, a bias current with a desired quiescent current; biasing first and second control transistors with the bias current to generate first and second currents, respectively, wherein the first and second control transistors form a differential pair which receives first stage differential input signals; mirroring the first and second currents to first and second push transistors which are connected to first and second pull transistors in series, respectively; and biasing the first and second pull transistors with the mirrored first and second currents, respectively; wherein each pair of serial connected push and pull transistors are complimentary and the two pairs of push and pull transistors output second stage differential output signals.