Patents by Inventor De-Chuan Liu

De-Chuan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250083144
    Abstract: A biochip includes a substrate, an insulating layer, a semiconductor layer, a dielectric layer, a metal layer, and a protective layer. The semiconductor layer is disposed on the insulating layer and has a reaction region. The dielectric layer is disposed on the semiconductor layer and has a first opening. The metal layer is disposed on the dielectric layer and includes a source, a drain, and a wall structure. The wall structure surrounds the first opening, the source, and the drain. The protective layer is disposed on the metal layer and has a flat part, a protruding part, a second opening, and a third opening. The flat part surrounds and defines the second opening. The protruding part is disposed corresponding to the wall structure, and the protruding part surrounds and defines the third opening. The second opening connects the third opening and the first opening to expose the reaction region.
    Type: Application
    Filed: January 30, 2024
    Publication date: March 13, 2025
    Applicant: EPISIL TECHNOLOGIES INC.
    Inventors: Wen Ting Hsu, De Chuan Liu, Kuo Yu Li
  • Patent number: 6799152
    Abstract: The current invention provides a method for analyzing process variations that occur during integrated circuit fabrication. Critical dimension data is collected for each layer of the integrated circuit fabrication process for a period of time and a shift indicator that indicates variation in the critical dimension data for each layer of the integrated circuit fabrication process is calculated. A machine drift significance indicator is also calculated for each machine used in each layer of the integrated circuit fabrication process, and a maximum shift of mean value for each layer of the integrated circuit fabrication process is defined. The shift indicator, the maximum shift of mean value and the machine drift significance indicator are used to determine at least one likely cause of variation in critical dimension for each layer of the integrated circuit fabrication process.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: September 28, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Ping Chen, Shao-Chung Hsu, De-Chuan Liu, Jung-Kuei Lu, Cheng-Yi Lin, Ta-Hung Yang, Hsin-Cheng Liu, Mao-I Ting, Yih-Cheng Shih
  • Publication number: 20030227092
    Abstract: The present invention provides a method for forming a contact opening having a rounded corner. Because the corner of the formed contact opening is rounded, a conductive material that is free of voids can be formed within the contact opening. In the present invention, a dielectric layer and a patterned photoresist layer are sequentially formed on a substrate. An isotropic etching process and a main etching process are performed to form a contact opening in the dielectric layer. A photoresist descum process is performed to remove a portion of the photoresist layer. Then, a soft etching process is performed to form a rounded corner on the top of the contact opening. The contact opening can be substantially filled with a conductive layer.
    Type: Application
    Filed: June 5, 2002
    Publication date: December 11, 2003
    Inventors: De-Chuan Liu, Jung-Kuei Lu, Sheng-Shing Hwu