Abstract: Apparatus and methods for rotational frequency detection are disclosed. In one embodiment, a rotational frequency detector is configured to receive samples taken from a serial data stream and to generate a frequency up error signal or a frequency down error signal. The rotational frequency detector processes a first set of samples to generate first transition data, which may be stored in a memory. The rotational frequency detector processes a second and third set of samples to generate second and third transition data. The frequency up or frequency down error signal is generated based at least partly on the first, second or third transition data. This configuration can reduce the maximum operating frequency of the rotational frequency detector, thereby simplifying the rotational frequency detector design to a point that a conventional static digital CMOS circuit design flow can be used to design the rotational frequency detector.

Abstract: Apparatus and methods for rotational frequency detection are disclosed. In one embodiment, a rotational frequency detector is configured to receive samples taken from a serial data stream and to generate a frequency up error signal or a frequency down error signal. The rotational frequency detector processes a first set of samples to generate first transition data, which may be stored in a memory. The rotational frequency detector processes a second and third set of samples to generate second and third transition data. The frequency up or frequency down error signal is generated based at least partly on the first, second or third transition data. This configuration can reduce the maximum operating frequency of the rotational frequency detector, thereby simplifying the rotational frequency detector design to a point that a conventional static digital CMOS circuit design flow can be used to design the rotational frequency detector.

Abstract: A harmonic detector including a pattern detector circuit responsive to a clock signal and a data signal configured to detect a target bit pattern from said data signal, and a time-out circuit responsive to said pattern detector circuit configured to detect the absence of said target bit pattern during a predetermined time-out parameter for indicating when said clock signal exceeds said data signal by a factor of two or more.

Abstract: A rotational frequency detector system including a rotational frequency detector responsive to a data signal and a clock signal. The rotational frequency detector is configured to compare the frequency of the clock signal to the frequency of the data signal to define frequency up and frequency down signals that adjust the frequency of the clock signal to be equal to the frequency of the data signal. A step control system is responsive to the rotational frequency detector and a step clock signal and is configured to define predetermined pulse widths for the frequency up and frequency down signals.