Abstract: A solid state switch, comprising a first metal-oxide-semiconductor field-effect transistor (MOSFET). The first MOSFET has a first terminal, a second terminal, a bulk terminal and a gate terminal, and is configured to be switched between an on-state and an off-state. The solid state switch also comprises a second MOSFET in series with the first MOSFET. The second MOSFET has a first terminal, a second terminal, a bulk terminal, and a gate terminal. The second terminal of the first MOSFET is connected to the second terminal of the second MOSFET. The solid state switch comprises a first buffer comprises an output terminal coupled to the bulk terminal of the first MOSFET, and an input terminal coupled to the first terminal of the first MOSFET.

Abstract: A solid state switch, comprising a first field-effect transistor (FET). The first FET has a first terminal, a second terminal, a bulk terminal and a gate terminal, and is configured to be switched between an on-state and an off-state. The solid state switch also comprises a second FET in series with the first FET. The second FET has a first terminal, a second terminal, a bulk terminal, and a gate terminal. The second terminal of the first FET is connected to the second terminal of the second FET. The solid state switch comprises a first buffer comprises an output terminal coupled to the bulk terminal of the first FET, and an input terminal coupled to the first terminal of the first FET.

Abstract: A solid state switch, comprising a first field-effect transistor (FET). The first FET has a first terminal, a second terminal, a bulk terminal and a gate terminal, and is configured to be switched between an on-state and an off-state. The solid state switch also comprises a second FET in series with the first FET. The second FET has a first terminal, a second terminal, a bulk terminal, and a gate terminal. The second terminal of the first FET is connected to the second terminal of the second FET. The solid state switch comprises a first buffer comprises an output terminal coupled to the bulk terminal of the first FET, and an input terminal coupled to the first terminal of the first FET.

Abstract: A new field-effect transistor (FET) based switch for use in/with high voltage precision instruments is provided. The switch can enable leakage compensation. A switch comprises a first FET in series with a second FET, and a buffer with an output terminal and an input terminal. The drain terminal of the first FET is connected to the source terminal of the second FET. The input terminal is coupled to the drain terminal of the second FET. At least one of: the first FET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the first FET; and, the second SFET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the second FET.

Abstract: A new MOS based switch for use in/with high voltage precision instruments is provided. The switch can enable leakage compensation. The switch can comprise a MOS device and a compensation circuit coupled to the MOS device to replicate and compensate for the MOS device leakage, such that the switch appears not to leak current. The compensation circuit may comprise a sense device which acts as a scaled replica of the MOS device being compensated. The sense device's leakage current can then be measured, reproduced at the scale factor, and injected back to the drain terminal of the MOS device.

Abstract: A solid state switch, comprising a first metal-oxide-semiconductor field-effect transistor (MOSFET) comprising: a drain terminal, a source terminal, and a gate terminal. The MOSFET is configured to be switched between an on-state and an off-state. The solid state switch also comprises a second MOSFET in series with the first MOSFET and a buffer with an output terminal and an input terminal. The second MOSFET has a gate terminal, a drain terminal, and a source terminal. The drain terminal of the first MOSFET is connected to the source terminal of the second MOSFET. The input terminal is coupled to the drain terminal of the second MOSFET. At least one of: the first MOSFET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the first MOSFET; and, the second MOSFET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the second MOSFET.

Abstract: A new field-effect transistor (FET) based switch for use in/with high voltage precision instruments is provided. The switch can enable leakage compensation. The switch can comprise a FET device and a compensation circuit coupled to the FET device to replicate and compensate for the FET device leakage, such that the switch appears not to leak current. The compensation circuit may comprise a sense device which acts as a scaled replica of the FET device being compensated. The sense device's leakage current can then be measured, reproduced at the scale factor, and injected back to the drain terminal of the FET device.

Abstract: A phase locked loop (PLL) circuit includes a controlled oscillator circuit that is operative to generate an output clock signal responsive to an oscillator control signal according to a plurality of selectable transfer functions, and an oscillator control signal generator circuit that is operative to generate the oscillator control signal responsive to the output clock signal and a reference clock signal. The PLL circuit further includes a transfer function control circuit operative to transition operation of the controlled oscillator from a first one of the transfer functions to a second one of the transfer functions responsive to the oscillator control signal.

Abstract: Clock signal generators include an integrated circuit chip having a PLL-based or DLL-based clock driver therein. The clock driver is configured to support generation of a plurality of clock signals having different frequencies in a range between 1 and 1/N times a frequency of an internal clock signal and full-period programmable skew characteristic, where N is a positive integer greater than one. The clock driver also includes a divide-by-N clock generator that is configured to generate N divide-by-N clock signals that have the same frequency but are phase shifted relative to each other. This clock generator operates in response to a first skew signal having a frequency equal to the frequency of the internal clock signal. A one-of-N select circuit is provided. This select circuit is configured to select one of the N divide-by-N clock signals in response to a time unit position signal.

Abstract: Clock signal generators include an integrated circuit chip having a PLL-based or DLL-based clock driver therein. The clock driver is configured to support generation of a plurality of clock signals having different frequencies in a range between 1 and 1/N times a frequency of an internal clock signal and full-period programmable skew characteristic, where N is a positive integer greater than one. The clock driver also includes a divide-by-N clock generator that is configured to generate N divide-by-N clock signals that have the same frequency but are phase shifted relative to each other. This clock generator operates in response to a first skew signal having a frequency equal to the frequency of the internal clock signal. A one-of-N select circuit is provided. This select circuit is configured to select one of the N divide-by-N clock signals in response to a time unit position signal.