Patents by Inventor Dedong Han
Dedong Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9733900Abstract: The present disclosure discloses a full adder based on resistive-switching devices and an operation method thereof. A multi-bit full adder circuit is constituted by using a cross-bar array of resistive-switching devices, wherein data of standard sums is stored on the principle diagonal of the cross-bar array in a nonvolatile manner, and carry data is stored in adjacent units on both sides of the principle diagonal. The carry data is stored according to whether the storage loop (crosstalk loop) is turned on. With the present disclosure, the multi-bit full adder circuit is significantly simplified. Thereby, additional circuits for generating a carry signal are reduced, the circuit delay and chip area are decreased, and the adder has an ability of nonvolatile storage.Type: GrantFiled: December 31, 2013Date of Patent: August 15, 2017Assignee: PEKING UNIVERSITYInventors: Lifeng Liu, Yi Hou, Bing Chen, Bin Gao, Dedong Han, Yi Wang, Xiaoyan Liu, Jinfeng Kang, Yuhua Cheng
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Publication number: 20160313975Abstract: The present disclosure discloses a full adder based on resistive-switching devices and an operation method thereof. A multi-bit full adder circuit is constituted by using a cross-bar array of resistive-switching devices, wherein data of standard sums is stored on the principle diagonal of the cross-bar array in a nonvolatile manner, and carry data is stored in adjacent units on both sides of the principle diagonal. The carry data is stored according to whether the storage loop (crosstalk loop) is turned on. With the present disclosure, the multi-bit full adder circuit is significantly simplified. Thereby, additional circuits for generating a carry signal are reduced, the circuit delay and chip area are decreased, and the adder has an ability of nonvolatile storage.Type: ApplicationFiled: December 31, 2013Publication date: October 27, 2016Inventors: Lifeng Liu, Yi Hou, Bing Chen, Bin Gao, Dedong Han, Yi Wang, Xiaoyan Liu, Jinfeng Kang, Yuhua Cheng
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Patent number: 9058986Abstract: Designs and fabrication of a FinFET are provided. In one implementation, the fabrication can include forming a dielectric stripe on a substrate; implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate to an amorphous layer; forming an amorphous semiconductor layer on the substrate covering the dielectric stripe and recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer; processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions; forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer; removing the dielectric stripe between the spacers so that the spacers can be formed as Fin bodies.Type: GrantFiled: June 13, 2011Date of Patent: June 16, 2015Assignee: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOLInventors: Shengdong Zhang, Ruqi Han, Dedong Han
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Patent number: 8956926Abstract: Disclosed is a method for manufacturing a self-aligned metal oxide thin film transistor. According to the present invention, a metal oxide semiconductor layer having a high carrier concentration is formed, and then a channel region which is self-aligned with a gate electrode is oxidized by a plasma having oxidbillity so that the channel region has a low carrier concentration and the source and drain regions have high carrier concentrations while the resulting transistor has a self-aligned structure. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.Type: GrantFiled: June 13, 2011Date of Patent: February 17, 2015Assignee: Peking University Shenzhen Graduate SchoolInventors: Shengdong Zhang, Xin He, Yi Wang, Dedong Han, Jeng Han
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Publication number: 20140065779Abstract: Designs and fabrication of a FinFET are provided. In one implementation, the fabrication can include forming a dielectric stripe on a substrate; implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate to an amorphous layer; forming an amorphous semiconductor layer on the substrate covering the dielectric stripe and recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer; processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions; forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer; removing the dielectric stripe between the spacers so that the spacers can be formed as Fin bodies.Type: ApplicationFiled: June 13, 2011Publication date: March 6, 2014Applicant: Peking University Shenzhen Graduate SchoolInventors: Shengdong Zhang, Ruqi Han, Dedong Han
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Publication number: 20140011329Abstract: Disclosed is a method for manufacturing a self-aligned metal oxide thin film transistor. According to the present invention, a metal oxide semiconductor layer having a high carrier concentration is formed, and then a channel region which is self-aligned with a gate electrode is oxidized by a plasma having oxidbillity so that the channel region has a low carrier concentration and the source and drain regions have high carrier concentrations while the resulting transistor has a self-aligned structure. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.Type: ApplicationFiled: June 13, 2011Publication date: January 9, 2014Applicant: Peking University Shenzhen Graduate SchoolInventors: Shengdong Zhang, Xin He, Yi Wang, Dedong Han, Ruqi Han
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Publication number: 20130122649Abstract: Disclosed is a method for manufacturing a metal oxide thin film transistor. According to the method, an active layer having a high carrier concentration is formed, and then a channel region is oxidized by plasma having oxidbillity so that the channel region has a low carrier concentration while a source region and a drain region have high carrier concentrations. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.Type: ApplicationFiled: June 13, 2011Publication date: May 16, 2013Applicant: Peking University Shenzhen Graduate SchoolInventors: Shengdong Zhang, Xin He, Yi Wang, Dedong Han, Ruqi Han