Abstract: An example transceiver includes a resistor having a first terminal and a second terminal coupled to a communication bus terminal. The transceiver includes a first transistor having a control terminal, a first terminal coupled to the first terminal of the resistor, and a second terminal coupled to a common mode voltage terminal. The transceiver includes a second transistor having a control terminal, a first terminal coupled to the second terminal of the resistor, and a second terminal coupled to the common mode voltage terminal. The transceiver includes a first driver having a first terminal coupled to a ground terminal, a second terminal coupled to the second terminal of the first transistor and the second terminal of the second transistor, a third terminal coupled to the control terminal of the first transistor, and a fourth terminal coupled to the control terminal of the second transistor.

Abstract: In described examples, a device includes a bias voltage circuit, an output circuit, and multiple current source circuits. A first plurality of the current source circuits is coupled between a first output of the bias voltage circuit and a first input of the output circuit. A second plurality of the current source circuits is coupled between a second output of the bias voltage circuit and a second input of the output circuit. Each of the current source circuits includes first and second resistors, first and second switches, and a transistor. The first switch is coupled between a gate of the transistor and the bias voltage circuit. The second switch is coupled between the gate of the transistor and a first terminal of the transistor. The second terminal of the transistor is coupled to the output circuit.

Abstract: A bus transceiver circuit including a current source device, a current mirror coupled to the current source device, and a first transistor having a first control input and first and second current terminals. The bus transceiver circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal is coupled to the first control input at a first node. The fourth current terminal is coupled to the current mirror. A resistor is coupled between the first current terminal and the first node.

Abstract: In an example, a CAN transceiver includes a first transistor having a control terminal, having a drain coupled to a voltage supply terminal, and having a source. The CAN transceiver includes a second transistor having a drain coupled to a control terminal of the first transistor, a source coupled to the source of the first transistor, and a control terminal. The CAN transceiver includes a bias circuit coupled to the control terminal of the second transistor, the second transistor configured to convert the first transistor to a diode configuration responsive to detecting high voltage noise.

Abstract: An example transceiver includes a resistor having a first terminal and a second terminal coupled to a communication bus terminal. The transceiver includes a first transistor having a control terminal, a first terminal coupled to the first terminal of the resistor, and a second terminal coupled to a common mode voltage terminal. The transceiver includes a second transistor having a control terminal, a first terminal coupled to the second terminal of the resistor, and a second terminal coupled to the common mode voltage terminal. The transceiver includes a first driver having a first terminal coupled to a ground terminal, a second terminal coupled to the second terminal of the first transistor and the second terminal of the second transistor, a third terminal coupled to the control terminal of the first transistor, and a fourth terminal coupled to the control terminal of the second transistor.

Abstract: In some examples, a circuit includes a first transistor, a second transistor, a first resistor, and a digital logic circuit. The first transistor has a control terminal and first and second terminals. The second transistor has a control terminal and first and second terminals, the first terminal of the second transistor coupled to the second terminal of the first transistor. The first resistor has first and second terminals, the first terminal of the first resistor coupled to the control terminal of the second transistor, and the second terminal of the first resistor coupled to the first terminal of the second transistor.

Abstract: A controller area network (CAN) transceiver including a transmitter, a receiver, a wake-up receiver including an attenuator, a gain stage, a comparator, a pulse filter, and wake-up monitor logic. The gain stage includes an offset generation circuit, a common-gate amplifier, and first and second resistors. The first and second resistors are coupled between outputs of the attenuator to develop a common mode voltage. The offset generation circuit is referenced to the common mode voltage. The pulse filter can include start/stop logic, a transistor, a third resistor and a first capacitor coupled to one input of a second comparator, and a fourth resistor and a second capacitor coupled to another input of the second comparator.

Abstract: In an example, a CAN transceiver includes a first transistor having a control terminal, having a drain coupled to a voltage supply terminal, and having a source. The CAN transceiver includes a second transistor having a drain coupled to a control terminal of the first transistor, a source coupled to the source of the first transistor, and a control terminal. The CAN transceiver includes a bias circuit coupled to the control terminal of the second transistor, the second transistor configured to convert the first transistor to a diode configuration responsive to detecting high voltage noise.

Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.

Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.

Abstract: In an example, a CAN transceiver includes a first transistor having a control terminal, having a drain coupled to a voltage supply terminal, and having a source. The CAN transceiver includes a second transistor having a drain coupled to a control terminal of the first transistor, a source coupled to the source of the first transistor, and a control terminal. The CAN transceiver includes a bias circuit coupled to the control terminal of the second transistor, the second transistor configured to convert the first transistor to a diode configuration responsive to detecting high voltage noise.

Abstract: An analog duty-cycle detector includes: off-time detection circuitry; on-time detection circuitry; compare circuitry; and a controller. The off-time detection circuitry includes a first transistor and a first capacitor. The on-time detection circuitry includes a second transistor and a second capacitor. The compare circuitry has a first terminal, a second terminal, and a third terminal. The first terminal of the compare circuitry is coupled to a first terminal of the first capacitor. The second terminal of the compare circuitry is coupled to a first terminal of the second capacitor. The controller has a first terminal and a second terminal. The first terminal of the controller coupled to a control terminal of the first transistor. The second terminal of the controller coupled to the control terminal of the second transistor.

Abstract: An input/output (I/O) interface includes a resistance-to-current (R/I) converter; an internal resistor; first, second, and third current sources; first and second diodes; and a comparator. The R/I converter is coupled to an I/O pin and generates an output current based on an external resistance at the I/O pin during an analog operating mode. The internal resistor is coupled to the I/O pin and to ground. The first current source is coupled to the R/I converter circuit. The first diode is coupled to the R/I converter and to the I/O pin. The second current source is coupled to the R/I converter and the first diode and to ground. The second diode is coupled to the I/O pin and to the third current source. The comparator has inputs coupled to the I/O pin and to a reference voltage, and outputs a control signal indicative of a digital operating mode.

Abstract: In an example driver circuit, one of two current sources coupled between a supply voltage and one output node is disabled during a driver disable time period (tpz) while the other continues to operate during a pre-charge monopulse time period (td) within tpz. A third current source on the other side of the driver circuit and coupled to ground is also disabled during tpz. During td, the following components are enabled: a charge current source coupled between the supply voltage and a second output node; a pair of current switches respectively coupled to the output nodes; and a pair of pull-down switches respectively coupled to control terminals of the current switches. After tpz, during a compensation time period (tcomp), the current sources enabled during td are disabled and a compensation current source is enabled. After tcomp, the compensation current source is disabled.

Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.

Abstract: Structure and functionality reduce differential leakage current and compensate for differential capacitance discharge current from diode configurations to mitigate differential output polarity reversal that may occur in driver circuits. In an example driver circuit, one of two current sources coupled between a supply voltage and one output node is disabled during a driver disable time period (tpz) while the other continues to operate during a pre-charge monopulse time period (td) within tpz. A third current source on the other side of the driver circuit and coupled to ground is also disabled during tpz. During td, the following components are enabled: a charge current source coupled between the supply voltage and a second output node; a pair of current switches respectively coupled to the output nodes; and a pair of pull-down switches respectively coupled to control terminals of the current switches.

Abstract: An on-off keying (OOK) receiver circuit includes a band-pass filter and an envelope detector. The band-pass filter includes a high-pass filter, a low-pass filter, and a switch. The high-pass filter is configured to filter an OOK input signal. The low-pass filter is configured to filter an output signal of the high-pass filter. The switch is coupled to an output of the high-pass filter, and is configured to, with each cycle of the OOK input signal, dissipate energy stored in the band-pass filter. The envelope detector is configured to receive a filtered OOK input signal from the band-pass filter, and to generate an OOK output signal based on the filtered OOK input signal.

Abstract: An input/output (I/O) interface includes a resistance-to-current (R/I) converter; an internal resistor; first, second, and third current sources; first and second diodes; and a comparator. The R/I converter is coupled to an I/O pin and generates an output current based on an external resistance at the I/O pin during an analog operating mode. The internal resistor is coupled to the I/O pin and to ground. The first current source is coupled to the R/I converter circuit. The first diode is coupled to the R/I converter and to the I/O pin. The second current source is coupled to the R/I converter and the first diode and to ground. The second diode is coupled to the I/O pin and to the third current source. The comparator has inputs coupled to the I/O pin and to a reference voltage, and outputs a control signal indicative of a digital operating mode.

Abstract: An on-off keying (OOK) receiver circuit includes a band-pass filter and an envelope detector. The band-pass filter includes a high-pass filter, a low-pass filter, and a switch. The high-pass filter is configured to filter an OOK input signal. The low-pass filter is configured to filter an output signal of the high-pass filter. The switch is coupled to an output of the high-pass filter, and is configured to, with each cycle of the OOK input signal, dissipate energy stored in the band-pass filter. The envelope detector is configured to receive a filtered OOK input signal from the band-pass filter, and to generate an OOK output signal based on the filtered OOK input signal.

Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the control terminal voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the control terminal voltage at a second time rate that is smaller than the first time rate.