Patents by Inventor Deep Buch

Deep Buch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9471118
    Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: October 18, 2016
    Assignee: Intel Corporation
    Inventors: Deep Buch, Vivek Garg, Subramaniam Maiyuran
  • Publication number: 20150046736
    Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
    Type: Application
    Filed: March 3, 2014
    Publication date: February 12, 2015
    Inventors: Deep Buch, Vivek Garg, Subramaniam Maiyuran
  • Patent number: 8700937
    Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: April 15, 2014
    Assignee: Intel Corporation
    Inventors: Deep Buch, Vivek Garg, Subramaniam Maiyuran
  • Patent number: 8244985
    Abstract: Apparatus and methods relating to store operations are disclosed. In one embodiment, a first storage unit is to store data. A second storage unit is to store the data only after it has become detectable by a bus agent. Moreover, the second storage unit may store an index field for each data value to be stored within the second storage unit. Other embodiments are also disclosed.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: August 14, 2012
    Assignee: Intel Corporation
    Inventors: Vladimir Pentkovksi, Ling Cen, Vivek Garg, Deep Buch, David Zhao
  • Patent number: 8122308
    Abstract: In one embodiment, a controller can perform a secure clear of a poisoned indicator associated with an uncorrectable error (after recovery from the error). To this end, the controller may access a register storing an address of a memory location associated with indicator, determine whether the address corresponds to an entry in a table storing a list of such errors, and perform the clear based at least in part on the determination. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventor: Deep Buch
  • Publication number: 20100262855
    Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
    Type: Application
    Filed: April 6, 2010
    Publication date: October 14, 2010
    Inventors: Deep Buch, Vivek Garg, Subramaniam Maiyuran
  • Patent number: 7694161
    Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 6, 2010
    Assignee: Intel Corporation
    Inventors: Deep Buch, Vivek Garg, Subramaniam Maiyuran
  • Publication number: 20090327638
    Abstract: In one embodiment, a controller can perform a secure clear of a poisoned indicator associated with an uncorrectable error (after recovery from the error). To this end, the controller may access a register storing an address of a memory location associated with indicator, determine whether the address corresponds to an entry in a table storing a list of such errors, and perform the clear based at least in part on the determination. Other embodiments are described and claimed.
    Type: Application
    Filed: June 25, 2008
    Publication date: December 31, 2009
    Inventor: Deep Buch
  • Publication number: 20090144500
    Abstract: Apparatus and methods relating to store operations are disclosed. In one embodiment, a first storage unit is to store data. A second storage unit is to store the data only after it has become detectable by a bus agent. Moreover, the second storage unit may store an index field for each data value to be stored within the second storage unit. Other embodiments are also disclosed.
    Type: Application
    Filed: January 27, 2009
    Publication date: June 4, 2009
    Inventors: Vladimir Pentkovksi, Ling Cen, Vivek Garg, Deep Buch, David Zhao
  • Patent number: 7484045
    Abstract: A store operation architecture in which store operation latency and read-for-ownership (RFO) throughput are improved. Embodiments of the invention relate to a method and apparatus to improve store performance in a microprocessor by allowing out-of-order issuance of RFO operations and more efficiently using the store buffer latency periods.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: January 27, 2009
    Assignee: Intel Corporation
    Inventors: Vladimir Pentkovksi, Ling Cen, Vivek Garg, Deep Buch, David Zhao
  • Publication number: 20080005603
    Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Deep Buch, Vivek Garg, Subramaniam Maiyuran
  • Publication number: 20060212876
    Abstract: In one aspect of the invention is a method to synchronize accesses by multiple threads to shared resources. The method entails a first thread entering a processing queue to contend for a lock on a shared resource. If a second thread exists, where the second thread is currently executing code, then the first thread may execute the critical section of code if the second thread is not currently executing the critical section; or if the second thread is currently executing the critical section of code, then the first thread may continue to contend for ownership of the shared resource until the second thread relinquishes ownership of the shared resource, or until a yield count expires.
    Type: Application
    Filed: May 19, 2006
    Publication date: September 21, 2006
    Inventor: Deep Buch
  • Publication number: 20050273601
    Abstract: Embodiments of the present invention relate to a system and method for providing processing capacity on demand. According to the embodiments, a processor package has a plurality of processing elements. One or more of the processing elements may be made active in response to increased demand for processing capacity based on modifiable authorization information.
    Type: Application
    Filed: May 19, 2004
    Publication date: December 8, 2005
    Inventors: Deep Buch, Shivnandan Kaushik
  • Patent number: 6748512
    Abstract: A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 8, 2004
    Assignee: Intel Corporation
    Inventors: Deep Buch, Varghese George, Vladimir Pentkovski, Paul Zagacki, Edward Gamsaragan
  • Publication number: 20020073296
    Abstract: A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 13, 2002
    Inventors: Deep Buch, Varghese George, Vladimir Pentkovski, Paul Zagacki, Edward Gamsaragan
  • Publication number: 20020073264
    Abstract: An Integrated Co-Processor Configured as a PCI Device is described herein.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 13, 2002
    Inventors: Varghese George, Vladimir Pentkovski, Deep Buch, Paul Zagacki, Edward Gamsaragan
  • Patent number: 6369813
    Abstract: The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N1 polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M1 vertex coordinates corresponding entirely to the N1 polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M1 vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: April 9, 2002
    Assignee: Intel Corporation
    Inventors: Vladimir Pentkovski, Deep Buch, Michael K. Dwyer, Hsien-Hsin Lee, Hsien-Cheng E. Hsieh
  • Publication number: 20020008698
    Abstract: The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N1 polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M1 vertex coordinates corresponding entirely to the N1 polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M1 vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.
    Type: Application
    Filed: June 30, 1998
    Publication date: January 24, 2002
    Inventors: VLADIMIR PENTKOVSKI, DEEP BUCH, MICHAEL K. DWYER, HSIEN-HSIN LEE, HSIEN-CHENG E. HSIEH